Fairchild Semiconductor Corporation

James B Boomer

Oscar W Freitas

Steven M Macaluso

Michael L Fowler

Roy L Yarbrough

Nickole Gagne

Trenor F Goodell

Sean X Clark

An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

MIPI analog switch for automatic selection of multiple image sensors

A serializer/deserializer interfacing a keypad or keyboard to a processing system is illustrated. However, to minimize wires on intervening cables, a serializer and deserializer is inserted between the processor system and the keypad forming a virtual keypad. The processor scans the deserializer as if it were the keypad and the keypad is scanned by the serializer as if it were the processor. The serializer converts the scanning of the keypad into a serial bit stream and clock that is sent to the deserializer. The deserializer accepts the serial bit stream and reconfigures the data into a response that mimics the response of the physical keypad. In one embodiment an actual second keypad is formed in the deserializer and activated as the first keypad is activated.

Method and circuit for capturing keypad data serializing/deserializing and regenerating the keypad interface

MIPI analog switch for automatic selection of multiple inputs based on clock voltages

A system for interleaving high speed data and slower data that is serialized and delivered to a microprocessor. The typical source of the high speed data is a camera and the source of the slower data is a keyboard. The high speed data and the slower data, illustratively, are interfaced with a micro-processor in a parallel fashion. The present invention mirrors the parallel interface to the microprocessor, and mirrors the parallel interface to the sources of the high speed (camera) and slower (keypad) data. The present system formats parallel data from the sources and passes that data in serial form, typically with a clock, on a flexible cable that joins two sections of many cell phones or other hand held devices.

Method and circuit for interleaving, serializing and deserializing camera and keypad data

A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.

Method and circuit for changing modes without dedicated control pin

A circuit is described that detects high and low frequencies and additional clock frequencies and outputs a signal that indicates a high, a low frequency or an additional mode. When in the low frequency low frequency mode signals are regenerated free of any high frequency signals from appearing on the filtered low frequency clock line. The rising and falling edges of the input clock are low pass filtered separately and then combined to generate a low frequency clock or the additional input clock and that retains the input clock pulse width and duty cycle.

Frequency mode selection discriminator and low pass filter

An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.

Low speed, load independent, slew rate controlled output buffer with no DC power consumption

A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of data. Word data bits are framed and sent along with clock pulses that define when the bits may be reliably received. High speed, typically, CML logic is used for the transmission line drivers and together with the clock pulse, a data word is sent faster than the computer system can send the next word to the serializer/deserializer. The disclosure frames the word and detects the word end, whereupon the system is placed into the standby mode. In addition the serializer/deserializers may be placed in a master/slave arrangement where the slave can be arranged to use the master's clock to send word data bits back to the master.

Low power serdes architecture using serial I/O burst gating

A serializer and a deserializer are disclosed and shown operating singly or as a pair. The invention operates independently from any outside system reference clock. The inventive system provides an internal bit clock that serializes the data when sending and de-serializes the data when receiving. A bit clock or pulse travels with the data word bits to define when a bit is stable. The system uses word boundary bits operating with a bit clock to distinguish different data words, as described in the parent application. The system operates either synchronously or asynchronously with the base computer or other such digital system, including I/O devices. The invention finds use where new data to be sent is strobed into the serializer, but also where a change in the data bit content itself will cause the changed data to be loaded into the serializer and sent bit by bit. The system operates where new data is strobed or loaded by the serializer (not the base computer system) when the last data word has been sent. In this case a signal is generated when the last word has been sent in the serializer that causes new data to be loaded for sending. Half duplex and full duplex configurations as disclosed. Similar, corresponding operations occur at the deserializer.

Sending and/or receiving serial data with bit timing and parallel data conversion

A bi-direction voltage level translating switch that connects a higher voltage circuit to a lower voltage circuit without using a direction signal disclosed. The drive circuit for the gate of an MOS switch acts to clamp the lower voltage side of the translating switch limiting the lower voltage to a level compatible with the lower voltage circuitry connected to the lower voltage side. A pull up circuit is connected to the higher voltage side of the switch and further defines a threshold lower than the lower voltage. When the signal reaches the threshold the pull up circuit pull the higher voltage side up to the higher voltage. Again the drive on the gate of the switch prevents that higher voltage from reaching the lower voltage side. When the lower voltage side drives, through an on switch, the higher voltage side low, the pull up circuit is designed to be overcome by the lower voltage drive circuitry so that the higher voltage side goes low. When the threshold is reached going low the pull up circuitry is disabled. In a preferred embodiment, the pull up circuit provides a low impedance connection to the higher voltage to quickly drive the higher voltage side high, but the low impedance is active for a given amount of time, wherein the pull up circuitry reverts to a high impedance. The circuit is suitable for operating in virtually all computer systems including networked communications, displays, data bases, and the like.

Active voltage level bus switch (or pass gate) translator

A translation switch is described with a transfer MOS transistor that connects a first node to second node where the first node is referenced to a higher voltage than is the second. A pseudo-rail generator drives the gate of the MOS transistor and provides a p-rail reference voltage lower in voltage to that of the first node. The generator includes a selectively enabled active clamping circuit that clamps the gate of the MOS transfer transistor to the p-rail potential and sinks current from the p-rail when higher voltages appear on the p-rail to thereby maintain the p-rail at a substantially constant potential.

Growing community of inventors

Monument, CO, United States of America

James B Boomer