Texas Instruments Corporation

James B Barton

Dennis D Buss

Stephen Perry Emmons

Tom F Cheek, Jr

A reduced-leakage current dynamic circuit ( ) is disclosed that includes a logic circuit ( ), a pre-charge transistor ( ), and a standby transistor ( ). The logic circuit ( ) is coupled to an internal output node ( ). The logic circuit ( ) includes a plurality of logic transistors ( and ) having a low threshold voltage. The pre-charge transistor ( ) is coupled to the internal output node ( ). The pre-charge transistor ( ) is operable to provide a pre-charge voltage at the internal output node ( ) and has a standard threshold voltage. The standby transistor ( ) is coupled to the internal output node ( ). The standby transistor ( ) is operable to provide a standby voltage at the internal output node ( ).

System and method for reducing leakage current in dynamic circuits with low threshold voltage transistors

A CCD memory is comprised of an array of serial-parallel-serial memory blocks. Each block is comprised of an N-stage serial-parallel register, an M-stage stack, and an N-stage parallel-serial register. The serial-parallel register has N outputs which couple in parallel to N inputs of the stack. The parallel-serial register has N inputs which couple in parallel to N outputs of the stack. Both registers have a zig-zag shaped charge transfer path which reduces their linear dimension, and also reduces the width of the stack.

Zig-zag SPS CCD memory

MOSFET structures are frequently used to establish the charge level in the first potential well of a CCD in accordance with an external voltage. When employed conventionally there exists a finite amount of charge under the MOSFET gate at the instant of turnoff. An indeterminate amount of this charge flows into the first potential well thereby giving rise to an uncertainty in the amount of charge in the well. Use of the invention disclosed eliminates this source of uncertainty.

CCD input and node preset method

A charge coupled device analog multiplexer in which a CCD shift register is characterized by an array of sets of phase electrodes. A plurality of charge packet injection input channels lead to an electrode in each of preselected sets in the array. A transfer gate common to all input channels admits charge packets to the array. A clock applies shift voltages to the array to move said charge packets to the multiplexer output where detector means responds to charge packets appearing at the output.

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Dallas, TX, United States of America

James B Barton