Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Freescale Semiconductor,inc.

Compaq Information Technologies Group, L.p.

James Arthur Farrell

Daniel Lawrence Leibholz

Bruce Alan Gieseke

Timothy Charles Fischer

Harry Ray Fair, Iii

Nevine Nassif

Derrick R Meyer

Sharon Marie Britton

Edward J McLellan

David J Husak

Nicholas Lee Rethman

Donald A Priore

Mark A Sankey

Madhav Desai

Andrew T Brown

Roy Badeau

John F Brown

Gill Watt

Thomas B Brightman

Paul Schmitt

Andrew D Funk

Dale Hayward Hall

Sven Eric Meier

In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K&#x2212;2, the number of instructions issued for cycle K&#x2212;1 and the number of instructions speculatively issued in cycle K&#x2212;1 that have produced a cache hit, and subtracting from the sum the number of instructions enqueued for cycle K&#x2212;1. The result indicates the number of invalid instructions in the queue cycle K. The number of invalid entries instructions, the number of issued instructions, and the number of enqueued instructions are preferably represented as flat vectors, so that adding is performed by shifting in one direction, while subtracting is performed by shifting in the opposite direction. The result is compared with either the number of instructions to be enqueued in the present cycle, which number is encoded, or with a predetermined value. A stall signal is generated if the indicative value is less than the encoded number or the predetermined value.

Method and circuits for early detection of a full queue

An integrated circuit () for use in processing streams of data generally and streams of packets in particular. The integrated circuit () includes a number of packet processors (), a table look up engine (), a queue management engine () and a buffer management engine (). The packet processors () include a receive processor (), a transmit processor () and a risc core processor (), all of which are programmable. The receive processor () and the core processor () cooperate to receive and route packets being received and the core processor () and the transmit processor () cooperate to transmit packets. Routing is done by using information from the table look up engine () to determine a queue () in the queue management engine () which is to receive a descriptor () describing the received packet's payload.

High speed and high throughput digital communications processor with efficient cooperation between programmable processing components

Digital communications processor

The present invention relates to a method and apparatus for determining capacitances and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

Timing verifier for MOS devices and related method

A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor select signals are generated from the flat vector counts for the N rows above and including the present row, and from the validity indicators associated with the N rows, where N is a predetermined value. A multiplexor associated with a particular row selects one of the N rows according to the select value, and moves or passes the instruction held in the selected row to the present row. A row's select value is determined by forming a diagonal from the N count vectors corresponding to the N rows above and including the present row, and logically ANDing, each diagonal bit with the valid bit associated with the same row. Each row's count vector is determined in two stages. In the first stage, a local count is determined for each row in a local group of rows, and a global count is determined for the entire local group. Each local count is determined by counting the validity indicators associated with rows in the local group. In the second stage, a final count is determined for each row in the queue, by combining the local and global counts generated for the local group in the first stage, with global counts generated in local groups below the local group. The N rows can extend to the queue's input pipeline.

Method for compacting an instruction queue

A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the physical registers. The technique further involves maintaining, in a vector memory circuit having bits that respectively correspond to the physical registers, a valid vector that forms, in combination with the list of register assignments, a list of valid register assignments. Furthermore, the technique involves storing, for an instruction that is mapped by the data processor, a copy of the valid vector from the vector memory circuit to a silo memory circuit. Preferably, the processor using the technique has the ability to execute branches of instructions speculatively, and to recover if it is determined that the processor executed down an incorrect instruction branch.

Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list

A system for accurately determining Elmore delays in DCVSL structures is disclosed. The system uses circuit simulation to determine models for Elmore delays through devices within specific circuit structures. The circuit structures include DCVSL circuits to accurately model performance of devices with such a structure. The system also determines discharge characteristics for DCVSL circuits using simulation. In order to determine Elmore delays, the system analyzes a circuit representation to locate DCVSL structures. The discharge characteristics and models are used to determine Elmore delays for each structure located.

Method and apparatus for performing timing verification of a circuit

In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K&minus;2, the number of instructions issued for cycle K&minus;1 and the number of instructions speculatively issued in cycle K&minus;1 that have produced a cache hit, and subtracting from the sum the number of instructions enqueued for cycle K&minus;1. The result indicates the number of invalid instructions in the queue cycle K. The number of invalid entries instructions, the number of issued instructions, and the number of enqueued instructions are preferably represented as flat vectors, so that adding is performed by shifting in one direction, while subtracting is performed by shifting in the opposite direction. The result is compared with either the number of instructions to be enqueued in the present cycle, which number is encoded, or with a predetermined value. A stall signal is generated if the indicative value is less than the encoded number or the predetermined value

The present invention relates to a method and apparatus for determining capacitance and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

A method and apparatus for determining load capacitance of DCVSL circuits in timing verification of a circuit is disclosed in the present invention. The gate capacitances for various MOS devices are modeled based upon simulations with certain conditions for inputs to the gate, source and drain. The system then determines the existence of DCVSL circuits within the topology of a circuit, and applies one of several models to determine minimum and maximum capacitances for the encountered DCVSL structures. The determination of minimum and maximum capacitance depends upon the selected model and the capacitance of each of the MOS devices as previously calculated.

Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL)

Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list

An arbiter system for the instruction issue logic of a CPU has at least two encoder circuits that select instructions in an instruction queue for issue to first and second execution units, respectively, based upon the positions of the instructions within the queue and requests by the instructions for the first and/or second execution units. As a result, since the instruction can request different execution units, this system is compatible with architectures where the execution units may have different capabilities to execute different instructions, i.e., each integer execution unit may not be able to execute all of the instructions in the CPU's integer instruction set. According to the present invention, one of the encoder circuits is subordinate to the other circuit. The subordinate encoder circuit selects instructions from the instruction queue based not only on the positions of the instructions and their requests, but the instruction selection of the dominant encoder circuit.

Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle

Instruction issue logic is disclosed that assesses register availability. The issue logic comprises register scoreboard logic that includes destination register storage elements to identify destination registers of instructions queued for issue. An arbiter selects instructions for issue during a machine cycle from the queued instructions. Register-clean wires associated with each register are driven in response to the corresponding destination storage elements and the arbiter. These wires are used to identify the read-availability of registers. Specifically, such a logic system is capable of reflecting freed registers on the subsequent machine cycle so that previously issued instructions do not hinder queuing of new instructions, unless they require multiple cycles to complete. To increase speed of operation, single NMOS devices bridge the register-clean wires and the issue signal from the arbiter. Addition speed increase may be achieved by dividing the register scoreboard logic into odd and even register scoreboard arrays on either side of the arbiter.

Register scoreboard logic with register read availability signal to

A technique for processing register instructions in a pipeline data processor in which multiple instructions may be processed concurrently, and may therefore conflict with one another. Register instructions are identified with register groups indicating which processor registers are affected by the execution of the register instruction. The progress of the execution of the register instruction is then controlled depending upon the identified register groups, in order to avoid conflicts with other concurrently processed instructions.

Technique for ordering internal processor register accesses

A technique for speculatively issuing instructions using an out-of-order processor. A cache miss by a load instruction results in either a reissue of all subsequently issued instructions for an integer instruction stream, or a reissue of only truly dependent instructions for a floating point instruction stream. One version of the technique involves issuing and executing a first instruction, and issuing a second instruction during a speculative time window of the first instruction that occurs after the first instruction is issued. The technique further involves executing the issued second instruction when the first instruction is executed in a first manner, and reissuing the second instruction and executing the reissued second instruction when the first instruction is executed in a second manner that is different than the first manner.

Growing community of inventors

Harvard, MA, United States of America

James Arthur Farrell