Lsi Logic Corporation

Silicon Space Technology Corporation

James Arnold Jensen

Jonathan W Byrn

Michael Norris Dillon

Richard D Blinne

Bret Alan Oeltjen

David R Gifford

Kevin Atkinson

David A Morgan

Matthew Scott Wingren

Donald Gabrielson

Christopher J Tremel

Roy Perrigo

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.

Memory circuit incorporating error detection and correction (EDAC), method of operation, and system

A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.

Latch-based random access memory

A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

Custom clock interconnects on a standardized silicon platform

The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration ('test backplane') for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the 'test backplane'. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the &#x201c;test backplane&#x201d;. These pre-exiting test structures may then be connected.

Method and apparatus for automatically configuring and/or inserting chip resources for manufacturing tests

A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an area cut out of the child macro corresponding to the location of the cell.

Growing community of inventors

Eagan, MN, United States of America

James Arnold Jensen