Cirrus Logic Inc.

Ami Semiconductor, Inc.

James Antone

Rahul Singh

Daniel O Gudmundson

John L Melanson

Ahsan Habib Chowdhury

Shyam S Somayajula

Krishnan Subramoniam

Brian R Kauffmann

Daniel Gudmondson

Melvin W Stene

Ahsan Habib Chowdury

A method of separating a chroma data component from a video data stream includes determining a phase relationship between a color burst in digital video data samples of a composite video signal and a local clock signal which processes the digital video data samples. In response to determining the phase relationship, interpolation filtering is performed on the digital video data samples corresponding to first and second display lines to generate phase aligned video data samples. Adaptive filtering is then performed utilizing the phase aligned video data samples corresponding to the first and second display lines to separate the chroma component from the digital video data samples corresponding to the first display line.

Luminance/chrominance video data separation circuits and methods and video systems utilizing the same

A video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal reduces the buffer size required to compensate for line-to-line variations in an unstable video source. A video signal is sampled at a predetermined rate and decimated by a selectable decimation factor prior to buffering. By selecting different decimation factors, the effective length of the buffer is changed from short duration for stable input signals and to longer duration for unstable input signals. A video signal quality detector is employed to provide a selection input that adjusts the decimation factor and also the loop bandwidth of a clock generator that provides the output clock for the buffer, which is generated from the input signal via a phase-lock loop (PLL). The operation of the system automatically varies from highly responsive for stable video input signals to less responsive for unstable video input signals, providing improved stability in the video output.

Video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal

A system in which drooping of the video levels due to leakage currents and proper DC bias level is addressed by providing a charge into the video signal to offset the leakage currents and to provide DC bias. To determine the leakage current level, measurements are made measuring the voltages of the syncs and the blanking intervals. To determine the DC bias, a measurement is made of the sync. Over a series of video lines these measurements are averaged. If the average is below the desired level, a charge is provided via a current source to the incoming signal. By having the current source provide charge during each video line, droop is reduced and the proper DC bias is provided.

Method and apparatus for AC coupling a signal while restoring DC levels

Method and apparatus to interface video signals to a decoder to compensate for droop

Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.

Method and apparatus to improve decoding of composite video signals

An adaptive circuit and method for separating luminance and chrominance components from a composite video signal by deriving three input lines from the composite video signal, determining whether any luminance similarity exists among the three input lines, and then selectively enabling a component filter based on any luminance similarity. If no luminance similarity exists among all three of the input lines, then a subtractive comb filter is enabled to maintain high vertical luminance resolution. If luminance similarity exists among all three of the input lines, then an additive comb filter is enabled. The additive comb filter performs three-line averaging when a high degree of similarity exists among all three consecutive input lines to minimize cross-chroma artifacts on lines that are similar. Chrominance similarity among the three input lines can also be determined by generating first and second chrominance values using different pairs of the three input lines, computing a difference of the first and second chrominance values, and comparing the chroma difference to a threshold value. If no luminance similarity exists between any of the three input lines or no chrominance similarity exists (i.e., there is vertical chroma transition), then a notch filter incorporated into the subtractive comb filter can be enabled.

Adaptive circuit for Y-C separation

A delay lock loop circuit is disclosed which includes a delay block which receives the clock signal and delays the clock signal by a selected amount to generate the delayed clock signal. A phase detector receives the clock signal and the delayed clock signal, compares the phases of the two signals and generates a phase comparison signal. A lock detector receives the clock signal and the delayed clock signal, compares the timing of the two signals and generates a potential lock indication signal. A controller receives the phase comparison signal and the potential lock indication signal and provides a delay control signal to the delay block to change the selected delay amount in response to the phase comparison signal. The controller interrupts the clock signal to the delay block for a selected interval in response to the potential lock indication signal, and generates a true lock indication signal in response to the potential lock indication signal after the interruption of the clock signal to the delay block. The delay lock loop circuit is capable of handling a wide range of clock frequencies and a step increase or decrease in the clock frequency.

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Austin, TX, United States of America

James Antone