International Business Machines Corporation

Jsr Corporation

James Anthony Tornello

Mahadevaiyer Krishnan

Tatsuya Yamanaka

Dinesh Kumar Penigalapati

Tatsuyoshi Kawamoto

Yohei Oishi

Rachel S Steiner

John Michael Cotte

Richard Paul Volant

Donald Francis Canaperi

Michael F Lofaro

Henry A Beveridge

Hariklia Deligianni

Christopher Vincent Jahnes

Panayotis Constantinou Andricacos

Kenneth Jay Stein

John Harold Magerlein

Jennifer L Lund

Michael A Cobb

L Paivikki Buchwalter

Soon-Cheon Seo

Paul Stephen Andry

Kevin Shawn Petrarca

Edmund Juris Sprogis

Jon Alfred Casey

Eric Jeffrey White

Carlos Juan Sambucetti

Eric D Perfecto

Cornelia K Tsang

Raymond R Horton

William J Cote

Max Gerald Levy

Seshadri Subbanna

Rangarajan Jagannathan

Matthew J Sendelbach

Cornelia Kang-I Tsang

Leena Paivikki Buchwalter

Judith Marie Rubino

Xiaomeng Chen

William C Wille

Dennis G Manzer

Kenneth M Davis

Michael Berger

Scott Alan Estes

Michael T Brigham

Joseph Thomas Kocis

Edward Jack Gordon

Michael Joseph MacDonald

James Hannah

Dinesh R Koli

Anurag Jain

Dean Allen Schaffer

George James Slusser

Uma Satyendra

Paraneetha Poloju

Michael Francis Lofaro

A chemical mechanical planarization for indium phosphide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. An indium phosphide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The indium phosphide material is planarized using at least one slurry composition to form coplanar surfaces of the indium phosphide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the indium phosphide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of phosphine gas.

Indium phosphide smoothing and chemical mechanical planarization processes

Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.

Germanium smoothing and chemical mechanical planarization processes

A chemical mechanical planarization for a Group III arsenide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. A Group III arsenide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The Group III arsenide material is planarized using at least one slurry composition to form coplanar surfaces of the Group III arsenide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.

Group III arsenide material smoothing and chemical mechanical planarization processes

An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.

High-yield method of exposing and contacting through-silicon vias

A glass mold polishing structure and method. The method includes providing a polishing tool comprising mounting plate, a chuck plate over and mechanically attached to the mounting plate, and a pad structure over and mechanically attached to the chuck plate. A retaining structure is attached the chuck plate. A glass mold comprising a plurality of cavities is placed on the pad structure and within a perimeter formed by the retaining structure. A vacuum device is attached to the chuck plate. The vacuum device is activated such that a vacuum is formed and mechanically attaches the glass mold to the pad structure. The polishing tool comprising the glass mold mechanically attached to the pad structure is placed over and in contact with the polishing pad. The polishing tool comprising the glass mold is rotated. The glass mold is polished as a result of the rotation.

Glass mold polishing method and structure

A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400&#xb0; C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.

Method of forming noble metal contacts

Noble metal contacts for micro-electromechanical switches

Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Materials and method to seal vias in silicon substrates

Slurry compositions comprising an oxidizing agent, optionally a copper corrosion inhibitor, abrasive particles; surface active agent, a service of chloride and a source of sulfate ions.

Slurry for mechanical polishing (CMP) of metals and use thereof

A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer. Alternatively, the method includes forming a multilayer MEMS structure by photomasking processes to form a first metal layer, a second layer including a dielectric layer and a second metal layer, and a third metal layer. The core layer and the encapsulating layers are made of materials with complementary electrical, mechanical and/or magnetic properties.

MEMS encapsulated structure and method of making same

The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface of the dielectric layer, forming an alloy film on the upper surfaces of the conductors, and brush cleaning the upper surfaces of the conductors and the dielectric layer.

Process to increase reliability CuBEOL structures

Method for planarizing photoresist

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Cortlandt Manor, NY, United States of America

James Anthony Tornello