International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Globalfoundries Inc.

James Anthony Marcella

Robert Allen Drehmel

Kent Harold Haselhorst

Herman Lee Blackmon

John Michael Borkenhagen

Alan G Gara

Bulent Abali

Dong Chen

Paul William Coteus

Gerald Keith Bartley

Adam James Muff

Todd Edward Takken

William Paul Hovis

Martin Ohmacht

Russell Dean Hoover

Barry Marshall Trager

Michael K Gschwind

Valentina Salapura

Michael A Blocksome

Joseph D Ratterman

Philip Heidelberger

Bruce Martin Fleischer

Alexandre E Eichenberger

Thomas M Gooding

Robert William Wisniewski

Joseph Allen Kirscht

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Matthias Augustin Blumrich

Sameh W Asaad

Shawn Anthony Hall

John Kevin O'Brien

Thomas Winters Fox

Chen-Yong Cher

Peng Wu

David John Krolak

Charles David Wait

Sameer Kumar

Todd Alan Inglett

George L Chiu

Krishnan Sugavanam

Todd Alan Greenfield

Gerard Vincent Kopcsay

Jeffrey John Parker

Paul William Rudrud

Robert Matthew Senger

Noel A Eisley

David L Satterfield

Douglas R Miller

Craig Brian Stunkel

Rudolf Adriaan Haring

Amith R Mamidala

Yutaka Sugawara

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

Michael M Tsao

Lyle Edwin Grosbach

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Peder James Paulson

Gabor J Dozsa

Ralph E Bellofatto

Peter Boyle

Brant L Knudson

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Steven M Wheeler

Brian E Smith

Eric Oliver Mejdrich

David Arnold Luick

Giora Biran

Clarence Rosser Ogilvie

Mark Owen Maxson

Paul Eric Dahlen

David Alan Shedivy

Brian Thomas Vanderpool

Jamie Randall Kuesel

George Wayne Nation

William Thomas Flynn

Shmuel Winograd

Wayne Melvin Barrett

Charles S Woodruff

Douglas A Baska

Ming-i Mark Lin

Mark E Kautzman

Kenneth Claude Hinz

Russel Dean Hoover

Matthew Adam Cushing

Allen James Gavin

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.

Translation table and method for compressed data

A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content.

Method for generating a delta for compressed data

A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a unidirectional broadcast portion for broadcasting commands from the repeater. The input portion comprises a plurality of links running from different devices, wherein each link is less than the full width of the broadcast bus portion. A command is transmitted over the input portion in a plurality of bus cycles, and broadcast over the broadcast portion in a single bus cycle. Since multiple input links connect to the central command repeater, it is possible to keep the broadcast bus full notwithstanding the fact that multiple bus cycles are required to transmit an individual command on the input portion. Preferably, the links are arranged hierarchically, from processors to local repeaters, from local repeaters to the central repeater, and back again. Preferably, the central repeater globally arbitrates the bus, and once the bus is granted, the command propagates along each link at pre-defined clock cycles from bus grant. In the preferred embodiment, addresses/commands and data are transmitted on essentially separate paths having different topologies, and at different times, and are arbitrated separately.

Bus architecture employing varying width uni-directional command bus

An apparatus and method for providing a data eye monitor. The data eye monitor apparatus utilizes an inverter/latch string circuit and a set of latches to save the data eye for providing an infinite persistent data eye. In operation, incoming read data signals are adjusted in the first stage individually and latched to provide the read data to the requesting unit. The data is also simultaneously fed into a balanced XOR tree to combine the transitions of all incoming read data signals into a single signal. This signal is passed along a delay chain and tapped at constant intervals. The tap points are fed into latches, capturing the transitions at a delay element interval resolution. Using XORs, differences between adjacent taps and therefore transitions are detected. The eye is defined by segments that show no transitions over a series of samples. The eye size and position can be used to readjust the delay of incoming signals and/or to control environment parameters like voltage, clock speed and temperature.

Data eye monitor method and apparatus

A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.

Error correcting code with chip kill capability and power saving enhancement

A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.

Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes

A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.

Diagnostic interface architecture for memory device

A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.

Computer system architecture for a processor connected to a high speed bus transceiver

Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with the first command based upon a conflict with an access to the memory bank. The penalty, in many embodiments, may be calculated so the penalty expires when the memory bank and a data bus associated with the memory bank are available to process the first command. Then, the first command is queued and dispatched to an available sequencer after the penalty expires. After the first command is serviced, unexpired penalties of subsequent commands may be updated to reflect a conflict with the first command. Further embodiments select a command to dispatch from the commands with expired penalties, based upon priorities associated with the commands such as the order in which the commands were received and the command types.

Methods and systems for re-ordering commands to access memory

Growing community of inventors

Rochester, MN, United States of America

James Anthony Marcella