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Sony United Kingdom Limited

James Andrew Scott Angus

Peter Charles Eastty

Peter Damien Thorpe

Christopher Sleight

A signal processor for 1-bit signals comprises a fifth order Delta-Sigma Modulator (DSM) having an input for receiving a 1-bit signal and an output at which a processed 1-bit signal is produced by a quantizer. The quantizer receives a p-bit signal from a series of five signal integration stages. Each stage comprises a first 1-bit multiplier coupled to the input, a second 1-bit multiplier coupled to the output, an adder which sums the outputs of the coefficient multipliers and an integrator which integrates the output of the adder. A final stage comprises a coefficient multiplier and an adder. The adder sums the output of the coefficient multiplier and the output of the integrator of the preceding integration stage. The coefficients are chosen to provide an overall attenuation of the input signal and of the quantization noise produced by the quantizer. Reduction of quantization noise allows several DSMs to be connected in series by preventing the build-up of excess noise, which may compromise stability.

Signal processors

A signal processing system in which a differentially quantized digital signal is used, the digital signal having two bits which represent only three values, of which one value ( or ) is zero and the other two ( and ) values represent a positive value and a negative value respectively.

Signal processing system employing two bit ternary signal

A 1-bit nth order Delta Sigma Modulator where n is at least one comprises a linear signal processing section (,) which processes the 1-bit signal and produces a p bit output, a filter (,) which filters the p bit signal, an adder (,) a quantizer Q coupled to the output of the adder (,) to quantize a p bit signal to a 1-bit output signal, and a noise shaping section,which feeds the 1-bit output signal back to the adder

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Clifton, United Kingdom

James Andrew Scott Angus