Other

Synopsys, Inc.

Mentor Graphics Corporation

James Andrew Garrard Seawright

Jeremy Rutledge Levitt

Christophe Gauthron

Chian-Min Richard Ho

Ping Fai Yeung

Kalyana C Mulam

Ramesh Sathianathan

An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.

Clock model for formal verification of a digital circuit description

A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification tool. Such automatic selection of one or more simulation states reduces the set of all simulation states to a small subset, thereby to address the state space explosion problem. Depending on the embodiment, the programmed computer uses one or more criteria provided by a library and/or by the user, in making its selection of states. Such criteria may be based on a property (assertion/checker) of the digital circuit and/or a signal generated during simulation. Furthermore, after such criteria (also called 'primary criteria') are applied, the selected states may be pruned by application of additional criteria (also called 'secondary criteria') prior to formal analysis.

Selection of initial states for formal verification

Finite state machines (FSMs) are synthesized from hierarchical high-level descriptions and optimized. Partitions of the FSM are selected by scanning the nodes of the hierarchical description and assigning to each suitable node a metric based upon the reachability function of the FSM. The metric is an indicator of the desirability of using the partition of the FSM, corresponding to the node, as a region of the FSM upon which to apply FSM optimization techniques. Based upon the metric, certain partitions are selected for optimization. Optimization of a partition can include the steps of converting the partition to a state graph, state graph minimization and conversion back to an FSM. Any hierarchical high-level language is suitable for the present invention, provided that a correspondence between nodes of the high-level description and partitions of the FSM can be determined. Conversion of an FSM partition for the purposes of optimization is performed with pruning functions also derived from the FSM's reachability function.

Method and apparatus for optimized partitioning of finite state machines synthesized from hierarchical high-level descriptions

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Mountain View, CA, United States of America

James Andrew Garrard Seawright