Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Samsung Electronics Co., Ltd.

James Andrew Davis

Jonathan Jedwab

Kenneth Graham Paterson

Kenneth Kay Smith

Gadiel Seroussi

David Murray Banks

Stewart R Wyatt

Frederick A Perner

Stephen Morley

David H McIntyre

Kenneth James Eldredge

Sarah Morris Brandenberger

Simon Edwin Crouch

Terrel Munden

Miranda Jane Mowbray

A system for error correction coding and decoding information is disclosed. In one embodiment, the first and second encoders are each configured to encode the information, wherein the second encoder has a higher capability than the first encoder. First and second decoders are configured to recover the information, wherein the second decoder recovers the information encoded by the second encoder only if the first decoder cannot recover the information.

System for error correction coding and decoding

A method and apparatus for identifying uncorrectable Reed-Solomon codewords in the presence of Reed-Solomon codewords which may have errors and erasures and otherwise be correctable.

Identifying uncorrectable codewords in a Reed-Solomon decoder for errors and erasures

A memory card comprising an magnetic random access memory (MRAM) array that comprises a plurality of magnetic memory cells and a controller coupled to the MRAM array. The controller is configured to communicate with a host device, and the controller is configured perform an error correction function associated with at least one of the plurality of magnetic memory cells.

MRAM with controller

A system for configuring solid-state storage devices comprises a solid-state storage device and an error correction code (ECC) selection system. The ECC selection system is configured to automatically select a set of error correction code based on an error rate of the storage device. The ECC selection system is further configured to install the selected set of error correction code in the solid-state storage device.

System and method for configuring a solid-state storage device with error correction coding

A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical defects. At manufacture, the MRAN device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data, using either a parametric evaluation (step), or a logical evaluation (step) or preferably a combination of both. Failed cells are identified and a count is formed, suitably in terms of ECC symbolsthat would be affected by such failed cells (step). The count can be compared to a threshold (step) to determine suitability of the accessed storage cells and a decision made (step) on whether to continue with use of those cells, or whether to take remedial action.

Manufacturing test for a fault tolerant magnetoresistive solid-state storage device

A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, a set of test cells in a test row are used to predict failures amongst a set of cells of interest storing a block of ECC encoded data. Erasure information is formed from these predictions which identifies potentially unreliable symbols in the block of ECC encoded data, and the ability of a decoder to perform ECC decoding is substantially enhanced.

Method for error correction decoding in a magnetoresistive solid-state storage device

A magnetoresistive solid-state storage device (MRAM device) uses storage cellsarranged in many arraysto form a macro-arrayFor fast access times and to reduce exposure to physical failures, each unit of data (e.g. a sector) is stored with a few sub-units (e.g. bytes) in each of a large plurality of the arraysAdvantageously, the plurality of arraysare accessible in parallel substantially simultaneously, and a failure in any one array affects only a small portion of the data unit. Optionally, error correction coding (ECC) is employed to form encoded data with symbols which are stored according to preferred embodiments which further minimise exposure to physical failures.

Magnetoresistive solid-state storage device and data storage methods for use therewith

A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical failures. At manufacture, the device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data. The test comprises identifying failed cells where the failures will be visible in use for the generation of erasure information used in ECC decoding, by comparing parametric values obtained from the cells against one or more failure ranges, and includes performing a write-read-compare operation with test data to identify failed cells which will be hidden for the generation of erasure information in use. A failure count is formed based on both the visible failures and the hidden failures, to determine that the set of cells is suitable for storing ECC encoded data. The failure count is weighted, with hidden failures having a greater weighting than visible failures.

A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cellsof the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbolsin a block of ECC encoded datawhich, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells. Where the position of suspected failed symbolsis known from this erasure information, the ability of a decoderto perform ECC decoding is substantially enhanced.

Error correction coding and decoding in a solid-state storage device

Embodiments of the present invention provide a magnetic memory. In one embodiment, the magnetic memory comprises an array of memory cells configured to provide resistive states, and a read circuit. The read circuit is configured to sense a resistance through a memory cell in the array of memory cells to obtain a sense result and categorize the sense result into one of at least three different categories comprising a middle category situated between the resistive states.

Magnetic memory including a sense result category between logic states

A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. ECC encoded data is read and decoded to identify failed symbols. A failure history table is then updated to indicate columnsof an array of storage cellswhich are suspected to be affected by physical failures. Advantageously, erasure information is formed with reference to the failure history table, and the ability of a decoderto perform ECC decoding is substantially enhanced.

Method for error correction decoding in an MRAM device (historical erasures)

A magnetoresistive solid-state storage device (MRAM) performs error correction coding (ECC) of stored information. Since currently available MRAM devices are subject to physical failures, data storage arrangements are described to minimize the affect of those failures on the stored ECC encoded data, including storing all bits of each symbol in storage cellsin one row(FIG.), or in at least two rowsbut using storage cellsin the same columns(FIG.). Sets of bits taken from each roware allocated to different codewords(FIG.) and the order of allocation can be rotated (FIG.). A second level of error checking can be applied by adding a parity bitto each symbol(FIG.).

Data storage method for use in a magnetoresistive solid-state storage device

A magnetoresistive state-solid state storage device having arrays of magnetoresistive storage cells. Sparing resources such as a plurality of spare rows are allocated to replace rows of storage cells which are affected by physical failures. A count is made for the number of failed rows within each array, and a count is also made of the number of failed rows within a cross-array row set spread across plural arrays. A spare row or rows are allocated by selecting a cross-array row set affected by the highest number of failed rows and therefore most likely to lead to unreliable data storage, and then selecting an array in this cross-array row set having the lowest number of failed rows, and therefore the least competition for sparing resources. The method proceeds iteratively with counts updated as sparing resources are allocated.

Allocation of sparing resources in a magnetoresistive solid-state storage device

In a coded orthogonal frequency division multiplex (COFDM) system n-bit data words are encoded as 2 -symbol code words, each symbol having 2 possible values (e.g. j&equals;3 for octary). An efficient decoder for these code words is provided by applying j iterations of the fast Hadamard transform, the input vector for the second and subsequent iterations being derived from the result of the immediately preceding iteration.

Methods and apparatus for decoding data

In a coded orthogonal frequency division multiplex (COFDM) system n-bit data words are encoded as 2 -symbol code words (binary, quaternary, octary, etc.). The code words are selected for desired low peak-to-mean envelope power ratio (PMEPR) characteristics of transmissions over a COFDM channel, from a set of cosets of a linear sub-code of a code having a specified generator matrix. The code words thus identified by the procedure described can, even for values of m in excess of 3, simultaneously limit the PMEPR to 3 dB, provide specified error control characteristics, be implemented in a feasible manner using analytical circuit techniques (e.g. with combinatorial logic), and include sufficiently many different code words to enable data to be transferred at useful rates. Other selections of code words can be made, enabling a higher maximum PMEPR or a reduced error detection capability to be accepted in order to obtain a higher code rate.

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Richmond, VA, United States of America

James Andrew Davis