Nxp Usa, Inc.

Freescale Semiconductor,inc.

James Andrew Collier Scobie

Alistair Robertson

Derek Beattie

Alan Devine

Carl Culshaw

David McMenamin

James Robert Feddeler

Graham Edmiston

Alison Young

Andrew Robertson

Alan R Duncan

Andrew Roberston

David Mcmenamin

A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.

Providing task-triggered deterministic operational mode for simultaneous multi-threaded superscalar processor

A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.

Method and apparatus for managing mismatches within a multi-threaded lockstep processing system

Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

Fault detection apparatus and method

An interrupt controller for controlling processing of interrupt requests by a plurality of processing units. The processing units have at least two modes: an active mode and an inactive mode. The interrupt controller comprises a controller input, an interrupt router coupled to the controller input and a monitoring unit. The monitoring unit outputs a routing change signal to the interrupt router if it determines that a selected processing unit, to which, in response to a received interrupt request, an execution of an interrupt service routine was initially routed, is in inactive mode while a preselected one is in the active mode. The interrupt router reroutes the execution of the interrupt service routine to the preselected processing unit.

Interrupt controller and a method of controlling processing of interrupt requests by a plurality of processing units

A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.

Method, system and integrated circuit for enabling access to a memory element

A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

Multi-core clocking system with interlocked 'anti-freeze' mechanism

A microcontroller unit comprises a reset controller operably coupled to a plurality of logic elements of the microcontroller unit. Low voltage detection logic is operably coupled to the reset controller and arranged to provide a plurality of low voltage interrupt signals to a number of respective logic elements of the microcontroller unit via the reset controller. A method of operating a microcontroller unit is also described.

Growing community of inventors

Helensburgh, United Kingdom

James Andrew Collier Scobie