International Business Machines Corporation

Mayo Foundation for Medical Education and Research

James Allen Rose

Timothy Hume Heil

Gary Scott Delp

Barry K Gilbert

Clifton R Haider

Andrew Henry Wottreng

Kimberly Marie Fernsler

Jason Nathaniel Dale

Jeffrey Powers Bradford

Richard James Eickemeyer

Steven R Kunkel

Timothy John Mullins

Harold F Kossman

Ross Evan Johnson

A system and method of dynamically localizing a measurement of parameter characterizing tissue sample with waves produced by spectrometric system at multiple wavelengths and detected at a fixed location of the detector of the system. The parameter is calculated based on impulse response of the sample, reference data representing characteristics of material components of the sample, and path lengths through the sample corresponding to different wavelengths. Dynamic localization is effectuated by considering different portions of a curve representing the determined parameter, and provides for the formation of a spatial map of distribution of the parameter across the sample. Additional measurement of impulse response at multiple detectors facilitates determination of change of the measured parameter across the sample as a function of time.

Spectrometric systems and methods for improved focus localization of time- and space-varying measurements

Spectrometric systems and mechanical methods for improved focus localization of time and space-varying measurements

Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit 'bypass type' field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.

Method to bypass cache levels in a cache coherent system

Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According to embodiments of the invention, attribute index bits may be included within a page table and may be used to determine page attributes stored within an attribute index. Additionally, embodiments of the invention provide a plurality of new page attributes.

Using an index value located on a page table to index page attributes

Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.

Multiple page size address translation incorporating page size prediction

A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize source identification information to selectively route data to different memory sources in a shared memory system. This permits, for example, data to be routed to only a portion of the memory sources associated with a given requester, thereby reducing the bandwidth to other memory sources and reducing overall latencies within the system. Among other possible information, the source identification information may include an identification of which memory source and/or which level of memory is providing the requested data, and/or an indication of what processor/requester and/or what type of instruction last modified the requested data.

Selective routing of data in a multi-level memory architecture based on source identification information

A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected point within the first thread is stored, execution of the first thread is terminated and a second thread is selected for execution only in response to a level two or higher cache miss, thereby minimizing processor delays due to memory latency. The validity state of each thread is preferably maintained in order to minimize the likelihood of returning to a prior thread for execution before the cache miss has been corrected. A least recently executed thread is preferably selected for execution in the event of a nonvalidity indication in association with all remaining threads, in anticipation of a change to the valid status of that thread prior to all other threads. A thread switch bit may also be utilized to selectively inhibit thread switching where execution of a particular thread is deemed necessary.

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Rochester, MN, United States of America

James Allen Rose