International Business Machines Corporation

Sony Computer Entertainment Inc.

Kabushiki Kaisha Toshiba

Motorola Corporation

Other

James Allan Kahle

Charles Ray Johns

Harm Peter Hofstee

Ravi Nair

Michael Norman Day

Hung Qui Le

Soummya Mallick

David James Shippy

Thuong Quang Truong

Aubrey Deene Ogden

Charles Roberts Moore

Philip Heidelberger

Chin-Cheng Kau

Michael K Gschwind

Dung Q Nguyen

Susan Elizabeth Eisen

Christopher Michael Abernathy

Peichun Peter Liu

Jeffrey Douglas Brown

Yuji Suzuki

Mary Douglass Brown

Albert J Loper, Jr

Shigehiro Asano

Hillery C Hunter

Sumedh Wasudeo Sathaye

Kevin Franklin Reick

Scott Douglas Clark

John-David Wellman

Erik Richter Altman

Edward John Silha

Larry Edward Thatcher

Peter George Capek

Takeshi Yamazaki

Donald E Waldecker

Martin Edward Hopkins

Cang Ngoc Tran

David S Levitan

Masakazu Suzuoki

Michael Fan Wang

David Scott Ray

Jaime Humberto Moreno

Robert Greg McDonald

James C Sexton

John Victor Sell

Abdullah Kayi

Changhoan Kim

Michael A Paolini

Dong Chen

Balaram Sinharoy

Michael Stephen Floyd

Hans Mikael Jacobson

Bruce Martin Fleischer

Burkhard Steinmacher-Burow

Lee Evan Eisen

Albert James Van Norstrand, Jr

Thomas Winters Fox

Atsushi Kunimatsu

Francis Patrick O'Connell

Michael John Mayfield

Pradeep Kumar Dubey

Robert Matthew Senger

David John Craft

Noel A Eisley

Alvan Wing Ng

Yutaka Sugawara

Jose R Brunheroto

Fabrizio Petrini

Gianfranco Gerosa

Michael C Alexander

Peichum Peter Liu

William John Starke

Renato John Recio

Hubertus Franke

Travis M Grigsby

Steven Robert Hetzler

Harold Wade Cain, Iii

George McNeil Lattimore

Martin Ohmacht

John Stephen Muhich

Alexander Erik Mericas

Brian R Konigsburg

Guerney D H Hunt

Hoichi Cheong

Jose Angel Paredes

Larry Scott Leitner

John Edward Derrick

Michael Putrino

Bernard Metzler

Tsutomu Horikawa

Eran Gampel

Alessandro Morari

H Peter Hofstee

Arturo Martin-de-Nicolas

Richard R Oehler

Russell A Reininger

Gregory F Grohoski

Larry Bryce Phillips

Ravinder Reddy Amanaganti

Robert Thaddeus Golla

A computer-implemented method includes, receiving, by a source node, a request from a destination node for data stored in a region of shared memory controlled by the source node. The data is encrypted in a local key of the source node. The method includes decrypting, by the source node, the locally encrypted data using the local key and encrypting, by the source node, the decrypted data using a first key for generating first encrypted data. The method also includes encrypting, by the source node, the first encrypted data using a second key for generating second encrypted data, and sending, by the source node, the second encrypted data to the destination node. A computer program product includes one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media. The program instructions includes program instructions to perform the foregoing method.

Secure memory sharing

Embodiments for providing enhanced endpoint multicast emulation in a computing environment. One or more multicast operations may be executed on an overlay network using endpoint multicast emulation by using an overlay layer or a virtual extensible LAN ('VXLAN') layer to maintain control over one or more multicast groups.

Enhanced endpoint multicast emulation

An approach is disclosed that configures a computer system node from components that are each connected to an intra-node network. The configuring is performed by selecting a set of components, including at least one processor, and assigning each of the components a different address range within the node. An operating system is run on the processor included in the node with the operating system accessing each of the assigned components.

Disaggregated system domain

An approach is described that provides access to a named data element in a Coordination Namespace that is stored in a memory that is distributed amongst a set of nodes. A request of a name corresponding to the named data element is received from a requesting process and the approach responsively searches for the name in the Coordination Namespace. In response to determining an absence of data corresponding to the named data element, a pending state is indicated to the requesting process. In response to determining that the data corresponding to the named data element exists, a successful state is returned to the requesting process. In one embodiment, the successful state also includes providing the requesting process with access to the data corresponding to the named data element.

Access of named data elements in coordination namespace

An approach is disclosed that maintains a consistent view of a virtual address by a local node which writes a first value to the virtual address and, after writing the first value, establishes a snapshot consistency state of the virtual address. The virtual address is shared amongst any number of processes and the processes includes a writing process and other processes that read from the virtual address. After writing the first value, the writing process writes a second value to the virtual address. Even after writing the second value, the first value is still visible to the other processes.

Global virtual address space consistency model

A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

Dynamic update of the number of architected registers assigned to software threads using spill counts

A system and process for managing thread execution includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the threads. Data for the threads may be moved between the first-level registers and second-level registers for different modes of thread processing.

Thread transition management

An approach is disclosed that relocates a named data element. A request to move a name corresponding to the named data element is received from a first storage area in a Coordination Namespace to a second storage area in the Coordination Namespace. The first storage area has a first level of persistence, and the second storage area has a second level of persistence. The named data element exists in a Coordination Namespace that is allocated in a memory distributed amongst a plurality of nodes that include the local node and one or more remote nodes. The approach then creates a copy of the named data element in the second storage area.

Relocation and persistence of named data elements in coordination namespace

An approach is described that provides a distributed directory structure within a storage of an information handling system (a local node). A request is received with the request corresponding to a shared virtual address. The shared virtual address that is shared amongst a number of nodes that includes the local node and some remote nodes. A Global Address Space Directory (GASD) is retrieved that corresponds to a global virtual address space. The GASD is stored in a Coordination Namespace that is stored in a memory that is distributed amongst the nodes. A mapping that is included in the GASD is used to determine the node where the shared virtual address currently resides. The shared virtual address is then accessed from the node where it currently resides.

Distributed directory of named data elements in coordination namespace

An approach is described that accesses data in a shared memory that is shared amongst nodes that include a local node and remote nodes. The local node receives a name corresponding to a named data element in a Coordination Namespace, the Coordination Namespace having been created in a memory distributed amongst the nodes. A hash function is applied to at least a portion of the name with a result of the hash function being a natural node indicator. Data corresponding to the named data element is requested from a natural node identified by the indicator. Based on the request, a response is received from the natural node.

Coordination namespace processing

An approach is disclosed that tracks memory transactions by a node. The approach establishes a transaction processing state corresponding to common virtual addresses accessed by a processing threads. Transactions are executed by the threads. A selected transaction is allowed to complete. In response to detecting a conflict in the transaction processing state, completion of a non-selected transaction is inhibited.

Tracking transactions using extended memory features

A system and process for managing thread transitions includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A determination is made whether a quantity of the first-level registers needed to execute one or more threads exceeds a quantity of the first-level registers of the two data register sets. Responsive to determining that the quantity of the first-level registers needed to execute the one or more threads exceeds the quantity of the first-level registers of the two data register sets, a portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the one or more threads.

According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.

Remote processing and memory utilization

A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Implementing selective cache injection

A system and process for managing thread transitions includes determining that a transition is to be made regarding the relative use of two data register sets where the two data register sets are used by a processor as first-level registers for thread execution. Based on the transition determination, a determination is made whether to move thread data in at least one of the first-level registers to second-level registers. Responsive to determining to move the thread data, a portion of main memory or cache memory is assigned as the second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing a thread. The thread data from the at least one first-level register is moved to the second-level registers based on the move determination.

Growing community of inventors

Austin, TX, United States of America

James Allan Kahle