International Business Machines Corporation

Hewlett Packard Enterprise Development LP

Texas Memory Systems, Inc.

James Alexander Fuxa

Charles John Camp

Holloway H Frost

Lance W Shelton

Timothy J Fisher

Yovita Iskandar

Michelle Geppert

Joseph Foster

Robert C Elliott

Han Wang

Thierry Fevrier

David Kimler Altobelli

Justin Haanbyull Park

Edgar Hance

Mark Barlow Hammer

Justin C Haggard

Sivathevan Maheswaran

Marc W Galloway

Keith Orsak

An example memory system may include a central processing unit (CPU) comprising a CPU cache, a storage class memory, a volatile memory and a memory controller. The memory controller is to store, in the storage class memory, a first cache line including first data and a first directory tag corresponding to the first data. The memory controller is to further store, in the storage class memory, a second cache line including second data and a second directory tag corresponding to the second data. The memory controller is to store, in the volatile memory, a third cache line that comprises the first directory tag and the second directory tag, the third cache line excluding the first data and the second data.

Volatile memory cache line directory tags

A system for achieving memory persistence includes a volatile memory, a non-volatile memory, and a processor. The processor may indicate a volatile memory range for the processor to backup, and open a memory window for the processor to access. The system further includes a power supply. The power supply may provide power for the processor to backup the memory range of the volatile memory. The processor may, responsive to an occurrence of a backup event, initiate a memory transfer using the opened memory window. The memory transfer uses the processor to move the memory range of the volatile memory to a memory region of the non-volatile memory.

Memory persistence from a volatile memory to a non-volatile memory

Example implementations relate to selectively enabling backup power to nodes. For example, a system includes a plurality of compute nodes, where each node includes a plurality of loads. The system also includes at least one backup power supply and control module coupled to the nodes and to the at least one backup power supply. The control module is to selectively enable an output of power from the at least one backup power supply to the nodes based on a comparison of a power capacity of the at least one backup power supply and a backup power demand of the nodes.

Selectively enabling backup power to nodes

Techniques for reducing power consumption of a storage controller are provided. An example method includes determining a back-end bandwidth of a storage system, wherein the back-end of the storage system includes a storage drive communicatively coupled to a storage controller. The method also includes determining a front-end bandwidth of the storage system, wherein the front-end of the storage system includes a front-end bus coupling the storage controller to a host. The method also includes computing a target back-end memory bandwidth based on the back-end bandwidth and computing a target front-end memory bandwidth based on the front-end bandwidth. The method also includes reducing power consumption of the storage controller by reducing a clock frequency of a memory device of the storage controller based on the greater of the target back-end memory bandwidth and the target front-end memory bandwidth.

Storage system bandwidth determination

A backup power and load discovery system can include a shared backup power supply controlled by a backup power control module, and a node coupled to the shared backup power supply, wherein the node supports a plurality of loads and includes system firmware to determine a subset of the plurality of loads that are to be protected by the shared backup power supply; and the system firmware to communicate the subset between the node and the shared backup power control module.

Backup power and load discovery

Techniques to determine an adjustment to front end bandwidth of a server based on backend bandwidth and to adjust power consumption of an input/output (I/O) device.

Storage system bandwidth adjustment

Methods and apparatuses for enhanced protection of data stored in a non-volatile memory system involve a controller capable of adapting to the failure of one or more non-volatile memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different non-volatile memory device. The controller also detects failure of a non-volatile memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed non-volatile memory device.

Memory system with variable length page stripes including data protection information

Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.

Efficient reduction of read disturb errors

A failure of at least one of a plurality of drives of a redundant array of independent disks (RAID) is determined. A remainder of the plurality of drives of the RAID are remapped. A RAID level of the RAID is maintained, if the remainder of the plurality of drives are remapped.

Remap raid to maintain raid level

Efficient reduction of read disturb errors in NAND flash memory

Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.

Method and apparatus for performing enhanced read and write operations in a FLASH memory system

Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device.

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Houston, TX, United States of America

James Alexander Fuxa