International Business Machines Corporation

Globalfoundries Inc.

James Albert Slinkman

Alan Bernard Botula

Alvin Jose Joseph

Randy Lee Wolf

Richard A Phelps

John J Ellis-Monaghan

Theodore Gerard Van Kessel

Max L Lifson

Toshiharu Furukawa

Max Gerald Levy

Arne Watson Ballantine

Edward J Nowak

Mark David Jaffe

Yun Shi

Michel J Abou-Khalil

Dale Warner Martin

Philip V Kaszuba

Leon Moszkowicz

Charles W Koburger, Iii

David S Collins

Mark Charles Hakey

Jeffrey Scott Brown

Theodore James Letavic

Ramana Murty Malladi

Gerd Pfeiffer

Jeffrey D Gilbert

Glenn Robert Miller

Blaine Jeffrey Gross

Bruce Bennett Doris

David V Horak

Chung H Lam

Robert J Gauthier, Jr

Steven H Voldman

Qizhi Liu

Matthew Joseph Breitwisch

Alain F Loiseau

Randy William Mann

James Stuart Dunn

Howard Smith Landis

Werner A Rausch

Larry Alan Nesbit

Natalie Barbara Feilchenfeld

Peter H Mitchell

BethAnn Rainey

Sadanand Vinayak Deshpande

Emily Gallagher

Joseph R Greco

Lyndon Ronald Logan

Richard Steven Kontra

Stephen Scott Furkay

Peng Cheng

Dinh Dang

Louis M Kindt

George W Banke, Jr

Thai Doan

Michael Lawrence Gautsch

James M Robert

Juan A Chediak

Edward D Adams

Jennifer C Robbins

Howard Ted Barrett

Jessica Anne Levy

James M Never

Alan Frederick Norris

Andrew Deering

Jeffrey E Hanrahan

Toshihura Furukawa

Kevin Munger

William Savaria

Anthony K Stamper

Jack Allan Mandelman

Steven J Holmes

William R Tonti

Steven M Shank

Terence B Hook

Robert Mark Rassel

Xuefeng Liu

Hemantha Kumar Wickramasinghe

William F Clark, Jr

Michael Joseph Zierak

Stephen Arthur St Onge

David P Vallett

Martin Knaipp

Eric Adler

Leah M P Pastel

Rainer Minixhofer

Mark Eliot Masters

Georg Roehrer

Anthony C Speranza

Duane E Galbi

Hubert Enichlmair

James J Quinlivan

Judith H McCullen

John J Benoit

Donald Walter Rakowski

Richard E Wistrom

Pierre J Bouchard

Serge Biesemans

Clayton C Williams

Lloyd A Bumm

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Integrated circuit heat dissipation using nanostructures

Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

SOI-MOSFET gate insulation layer with different thickness

Semiconductor structures formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. One or more trench isolation regions are formed in the device layer that surround an active device region. An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer. A removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region.

Air gaps formed by porous silicon removal

Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.

Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming

Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set of trenches; a first oxide abutting the silicon substrate; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions; a gate structure overlying the second oxide between adjacent salicide regions; and a first contact contacting the gate structure; a second contact contacting one of the salicide regions; a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and an air gap in each of the set of trenches, the air gap surrounded by the third oxide.

An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate. The method also includes forming a transistor in a second portion of the SOI island. The method further includes electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island.

Silicon-on-insulator heat sink

Growing community of inventors

Montpelier, VT, United States of America

James Albert Slinkman