International Business Machines Corporation

James Albert Pieterick

Brent William Jacobs

Kraig Bottemiller

Harvey Gene Kiel

Devon D Snyder

Stephen T Eagen

Gregory Albert Dancker

Steven Joseph Amell

John Elliott Walker

William Van Durrett

Bruce Richard Culbertson

John Howard Botterill

Kevin Malachi Galloway

A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU). The auxiliary processor unit (APU) processes a trace instruction. When a trace instruction is identified by the APU, the APU signals the CPU with a pipeline stall signal for stalling the CPU and checks for an enabled trace engine as specified by the trace instruction. When the trace engine for the trace instruction is enabled, then the trace data is written into a trace buffer. The APU signals the CPU with an op done signal for allowing the CPU to continue with instruction processing.

Apparatus and computer program product for implementing atomic data tracing

Method, apparatus and computer program product for implementing atomic data tracing

A method and profiling cache for management of virtual memory includes a set of entries stored in the profiling cache. Each entry of the set of entries includes a page address, a time stamp for the page address and a least recently used (LRU) count; and the LRU count is updated for each access of the page address. Entries in the profiling cache are cast out using the LRU counts. A translation lookaside buffer (TLB) includes a first TLB section for storing a plurality of temporarily pinned entries and a second TLB section for storing a plurality of non-pinned entries. Responsive to a TLB interrupt, an entry is loaded in the second TLB section using a first in first out algorithm for replacing the non-pinned entries. The first TLB portion is periodically updated utilizing identified ones of the set of entries in the profiling cache having oldest time stamps.

Method and profiling cache for management of virtual memory

A method, apparatus and computer program product are provided for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory. A page table with page table entries (PTEs) is provided for mapping multiple sized pages from a virtual address space to a physical address space. Each of the multiple sized pages is a multiple of a base page size. A region of memory having a starting address and a length is divided into a minimum number of natural blocks for the memory region. Once the region of memory is divided into the natural blocks, page table entries (PTEs) are assigned to map each natural block. Multiple identical PTEs are required to map each natural block greater than a base page size. Only one TLB entry is used to map each natural block.

Method, apparatus and computer program product for dynamically minimizing translation lookaside buffer entries across contiguous memory

A computer system automatically senses characteristics of diverse peripheral devices connected to a common communications port, and automatically maximizes the communications speed with the devices. Coupled in daisy chain fashion to the communications port, all peripheral devices receive every signal issued from the controller port, each device responding only to signals addressed to that device or signals addressed to a universal address. The controller first receives an identifier from peripheral devices attached to the controller port. The controller then interprets the received identifiers to determine a maximum communications speed for each device. Next, the controller and the attached peripheral devices are configured to communicate at the maximum communications speed of the slowest device. This guarantees that all messages sent by the controller are compatible with all peripheral devices. Devices subsequently coupled to the communications port are considered by the controller, and the port and other devices are reconfigured as necessary to ensure the fastest possible communications speed.

Computer system with peripheral device characteristic sensing and

A method and system are disclosed which permit the presentation of single and double digit selection field in a non-programmable terminal. Multiple numeric characters associated with particular textual choices are coupled to a workstation controller interface along with an identified offset within each textual choice to a selected mnemonic character. If an associated terminal display device does not support more advanced graphic elements, such as so-called 'radio buttons' and underscored mnemonics, the numeric characters and textual choices are entered into a format table entry and utilized to specify a selection field within the terminal display. A single or double digit numeric indicator area is then defined within the terminal display and numeric entries within the selection field are displayed within the numeric indicator area, permitting the user to visually affirm what textual choice will be selected upon entry. A selected textual entry is then displayed utilizing highlighting or reverse video, providing a simulation of graphic entry techniques while permitting direct selection of any textual choice. If an associated terminal supports advanced graphic elements, the offset value is utilized to identify a selected mnemonic character within each textual choice and graphic input controls, such as 'radio buttons' are then utilized to indicate a selection of a textual choice.

Method and system for presentation of single and double digit selection

Growing community of inventors

Rochester, MN, United States of America

James Albert Pieterick