Adv Antest Corporation

James Alan Turnquist

Shigeru Sugamori

Rochit Rajsuman

Anthony Le

Hiroaki Yamoto

Glen Gomes

Robert F Sauer

Bruce R Parnas

Leon Lee Chen

Rochit Rajusman

An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.

Event based IC test system

A semiconductor test system which generates a test pattern produced based on data resultant to device logic simulation performed on a computer for an LSI device designed in an electronic design automation (EDA) environment, tests the LSI device, and feedbacks the test results to the EDA environment. The semiconductor test system includes an event file for storing event data obtained by executing device logic simulation in a design stage of an LSI device under test; an event memory for storing the event data from the event file relative to timings; means for generating a test pattern by directly using the event data from the event memory and applying the test pattern to the LSI device under test; a result data file for evaluating a response output of the LSI device under test and storing resultant evaluation data; and means for evaluating design of the LSI device based on the data stored in the result data file.

Event based semiconductor test system

An apparatus and method in an event based test system for testing an electronics device under test (DUT). The apparatus includes an event memory for storing timing data and event type data of each event wherein the timing data of a current event is expressed by a delay time from an event immediately prior thereto with use of a specified number of data bits, and an additional delay time inserted in the timing data of a specified event in such a way to establish a total delay time of the current event which is longer than that can be expressed by the specified number of data bits in the event memory. The additional delay time is inserted by replicating the timing data and the event type data of the event immediately prior to the specified event.

Apparatus and method for successively generating an event to establish a total delay time that is greater than can be expressed by specified data bits in an event memory

A semiconductor test system for testing a semiconductor device under test (DUT) is able to store failure data in a data failure memory with small memory capacity. The semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT, means for evaluating an output signal of the DUT and producing failure data when there is a fail therein, a data failure memory for storing the failure data, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of addresses of the pattern memory is stored in a corresponding address of the data failure memory, and for executing a second test operation for only a group of addresses of the pattern memory in which the failure data is detected without an address compaction.

Data failure memory compaction for semiconductor test system

An event based test system has a cost effective, error free, secure and simple way of managing the calibration data for all of the pin cards used therein. The test system has a large number of test channels for testing a semiconductor device under test (DUT) by applying test patterns to device pins of the DUT through the test channels and examining response outputs of the DUT. The test system includes a plurality of pin cards, each having a plurality of pin units therein to establish a part of the test channels, a non-volatile memory provided within each pin card for storing calibration data for compensating error factors involved in the pin units mounted in the corresponding pin card, and a microprocessor provided within each pin card for managing the calibration data and executing the calibration procedure for all of the pin units in the corresponding pin card, and wherein each pin unit is configured as an event tester in which a test, pattern or a strobe signal is directly generated based on event data stored in an event memory which define any changes from a previous event with reference to a time difference therefrom.

Event based test system storing pin calibration data in non-volatile memory

A single semiconductor test system which behaves as multiple logic testers, each operating separately and asynchronously from the other. The semiconductor test system includes a host computer for controlling an overall operation of the test system by executing a test program, a plurality of pin-units each having means for generating a test pattern to an assigned pin of a semiconductor device under test (DUT) and evaluating a resultant response of the DUT, a pin-unit bus provided between said host computer and the plurality of pin-units for transmitting data, address, control signals and clocks, and means for configuring the pin-units corresponding to input/output pins of devices under test when a group selection address is placed on the pin-unit bus by the host computer.

Semiconductor test system supporting multiple virtual logic testers

An event based test system is configured to test an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event formed with an integer multiple of a reference clock period and a fraction of the reference clock period wherein the timing data represents a time difference between a current event and a reference point, an address sequencer for generating address data for accessing the event memory, a timing count and scaling logic for generating an event start signal, an event generation unit for generating each event based on the event start signal and data indicating the fraction of the reference clock period, and a host computer for controlling an overall operation of the event based test system.

An event based test system for testing semiconductor devices under test (DUT). The event based test system is freely configured to a plurality of groups of sin units where each group is able to perform test operations independently from the other. The start and end timings of the test in each group are independently made by generating multiple end of test signals. The event based test system includes a plurality of pin units to be assigned to pins of the DUT, a signal generator for generating an end of test signal for indicating an end of current test which is generated for each pin unit independently from other pin units, and a system controller for controlling an overall operation in the event based test system by communicating with each pin unit. The end of test signal for each pin unit is selected by condition specified by the system controller and the selected end of test signal is provided to the system controller and to the other pin units.

Multiple end of test signal for event based test system

A semiconductor test system has a glitch detection function for detecting glitches in an output signal from a device under test to accurately evaluate the device under test (DUT) . The semiconductor test system includes an event memory for storing event data, an event generator for producing test patterns, strobe signals and expected patterns based on the event data from the event memory, a pin electronics for transmitting the test pattern from the event generator to the DUT and receiving an output signal of the DUT and sampling the output signal by timings of the strobe signals, a pattern comparator for comparing sampled output data with the expected patterns, and a glitch detection unit for receiving the output signal from the DUT and detecting a glitch in the output signal by counting a number of edges in the output signal and comparing an expected number of edges.

Glitch detection for semiconductor test system

An event based test system for testing an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event which represents a time difference between two adjacent events, an address sequencer for generating address data for accessing the event memory, a timing count logic for summing the timing data to produce an overall time of each event relative to a predetermined reference point, an event generation circuit for generating each event based on the overall time for formulating the test signal or strobe signals, and a host computer for controlling an overall operation of the event based test system.

Delta time event based test system

An event based test system for storing event data in a compressed form to reduce the size of a memory and decompressing the data to produce the events for testing a device under test (DUT). The event based test system includes a clock count memory for storing clock count data of each event wherein the clock count data is formed of one or more data words depending on the value of the integral part data, a vernier data memory for storing vernier data of each event wherein the vernier data memory stores vernier data for two or more events in the same memory location, an address sequencer for generating address data for accessing the clock count memory and the vernier data memory, a decompressor for reproducing the clock count data from the clock count memory and the vernier data from the vernier data memory corresponding to each event. The event based test system may further include an event process controller for producing an overall delay time of each event relative to a predetermined reference point based on the clock count data and vernier data from the decompressor, and a fine delay controller for generating each event based on the overall delay time to produce test signals for testing the DUT.

Event based test system data memory compression

A compression and decompression apparatus to be used for transferring test pattern data from a storage device of a host computer to a pattern memory in a semiconductor test system for testing a semiconductor device to decrease the time required for the data transfer. The compression and decompression apparatus includes: a compression means for classifying vector data in the test pattern data into a first group to be compressed to a short code and a second group not to be compressed, and for producing a look-up table showing relationship between the short code and the vector data in the first group; a compressed test pattern file storing compressed test pattern including the short code, data vector in the second group and the look-up table; and a hardware decompression circuit provided in the semiconductor test system or proximity thereto for decompressing the compressed test pattern based on the short code and the relationship shown in the look-up table and for sending decompressed test pattern to the pattern memory in the semiconductor test system.

Growing community of inventors

Santa Clara, CA, United States of America

James Alan Turnquist