Altera Corporation

Xilinx, Inc.

Advanced Micro Devices Corporation

James A Watson

L Todd Cope

Bahram Ahanin

Richard G Cliff

Joseph Huang

William W Leong

Cameron R McClintock

Cameron R Mc Clintock

Bruce B Pedersen

Francis B Heile

David Chiang

Hock-Chuen So

Michael A Margolese

Chiakang Sung

Wanli Chang

Fabiano Fontana

Fung Fung Lee

Yiu-Fai Chan

Ken Ming Li

Caleb Crome

Hiten S Randhawa

Chang-Chia Hsiao

Benjamin Lau

Steve Choi

Jenny Chui

The present invention relates to a system for communicating between two integrated circuits (ICs) or within an IC. The ICs are either on the same circuit boards or on different circuit boards with a common backplane. The system comprises a first integrated circuit having an output circuit for generating phase shift keying signals and a second integrated circuit having an input circuit for decoding the phase shift keying signals. The output circuit may include a ring oscillator for generating multiple clock signals that are phase-locked to one another.

Phase shift keying signaling for integrated circuits

The present invention relates to a system for communicating between two integrated circuits (ICs) or within an IC. The ICs are either on the same circuit boards or on different circuit boards with a common backplane. A first integrated circuit has transmitter circuit that generates frequency shift keying signals using digital data and a second integrated circuit has a receiver circuit for recovering the digital data from the frequency shift keying signals.

Frequency shift keying signaling for integrated circuits

A method of controlling an antenna system of a wireless communication network having a plurality of cells is disclosed. The method comprises the steps of determining antenna weights to enable communication between a wireless communication network and the wireless communication device within the wireless communication network; storing the antenna weights in a programmable memory associated with the wireless communication network; and providing predetermined stored antenna weights to the antenna system based upon a location of the wireless communication device. A circuit and wireless communication network for controlling an antenna system are also disclosed.

Method and circuit for controlling an antenna system

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ('LABs'). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Programmable logic array integrated circuits

A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.

Variable depth and width memory device

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ('LABs') The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

An enhanced method of testing semiconductor devices having nonvolatile elements by determining regions of the semiconductor having differing orders of probability that a defect will occur. The enhanced method of testing includes testing of regions from the highest probability to the lowest probability of having a defect. Nonvolatile memory elements in the region being tested are placed in a high impedance state, bypass circuits in the region being tested are activated to bypass the nonvolatile memory elements that control the state of elements in the region being tested and test vectors are applied to the elements that are controlled by the bypassed nonvolatile memory elements. This procedure is repeated for the next untested region having the highest probability of having a defect until all regions have been tested.

Enhanced method of testing semiconductor devices having nonvolatile

A system and method for making and using integrated circuits using a modeling system. The system utilizes a pin test buffer. The pin test buffer inputs external inputs to a pin, and outputs to the same pin from the device. If contention is noted between the system inputs to the pin, and outputs from the device to the pin, contention error notices are provided to the user.

Buffer for identification of pin contentions in circuit design and

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Santa Clara, CA, United States of America

James A Watson