Intel Corporation

James A Stone

Kiran A Padwekar

Keshavram N Murty

Andre E Wolper

A circuit and method for handling a hardware conflict experienced by a branch target buffer. The method for handling the hardware conflict includes three steps. First, a determination is made to detect whether there is a write allocation to a branch target buffer (BTB) cache. If so, precedence is given to the write allocation by invalidating at least a first instruction pointer within a BTB pipeline. The first instruction pointer would have been used to read information from the BTB cache for branch prediction, absent the write allocation. Thereafter, the first instruction pointer is recovered by reloading it into the BTB pipeline in order to avoid missing its opportunity to predict. The two cycle delay caused by the invalidation and recovery of the first instruction pointer has little effect on the performance level of the circuit practicing this method of operation.

System for recovering from a concurrent branch target buffer read with a

A programmable high watermark for a stack frame cache for eliminating frame spills initiated by certain critical events. A stack frame cache in a microprocessor is divided into two regions. The second region in the stack frame cache is reserved for context switches initiated by high priority events. Low priority events will result in a frame spill when the first region of the stack frame cache is filled. A high priority event will utilize the second region of the stack frame cache for a context switch if the first region is filled, thus eliminating the need for a reference to off-chip main memory.

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Phoenix, AZ, United States of America

James A Stone