Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Helwett-packard, Co.

James A Schinnerer

Jeffrey Joel Walls

Kevin T Lefebvre

Donley Byron Hoffman

Jason A Daughenbaugh

Byron Alan Alcorn

Robert James Martin

A system and method for configuring a plurality of graphics pipelines in a computer graphical display system is disclosed. The method comprises displaying a graphical user interface to enable a user to graphically specify at least one parameter for a plurality of pipe rectangles of the computer graphical display system, each of the plurality of pipe rectangles being associated with at least one of the plurality of graphics pipelines, receiving the at least one parameter, and updating a compositor of the computer graphical display system in real-time based at least in part on the at least one parameter.

System and method for configuring graphics pipelines in a computer graphical display system

A preferred method includes the steps of receiving the active stereo video data containing the right channel pixel data and the left channel pixel data corresponding to the image to be rendered, re-sequencing the right channel pixel data and the left channel pixel data, and simultaneously outputting corresponding frames of the right channel pixel data and the left channel pixel data for displaying the image to be rendered in passive stereo. Devices also are provided.

Systems and methods for rendering active stereo graphical data as passive stereo

A system for synchronizing video data streams utilizes a plurality of buffer pairs and buffering logic. The buffering logic is configured to receive image frames from a plurality of asynchronous video data streams and to perform comparisons between frame identifiers associated with the image frames. The buffering logic is further configured to double buffer the image frames via the plurality of frame buffer pairs based on the comparisons and to synchronously output the image frames from the frame buffer pairs.

System and method for sychronizing video data streams

In a computer graphics system, displaying any given graphics data on a monitor, the type of compression of screen data is chosen during processing. Further, the compression technique is allowed to vary on a per row basis within a block of pixels. The type of compression is encoded with the screen data and stored in screen memory. As the compressed graphics is read from screen memory just prior to display, the screen data is decompressed.

Real time control of multiple compression techniques within a graphics display subsystem

A sorting fifo for use in a memory controller of a graphics system is provided to rearrange the order of an incoming stream of pixels such that groups of pixels to the same page are grouped together. By rearranging the order of pixels before they are forwarded to a frame buffer memory, the repaging delays at the frame buffer memory may be minimized, and the overall performance of the graphics system is increased. The sorting fifo may include, for example, a pair of fifos coupled to a common controller. The controller is also coupled to the input address bus. The controller compares the page addresses of data received on the input address bus against page addresses of data references stored in the fifos. When there is a match, the data reference is forwarded to the appropriate fifo. The controller also controls the reading of data out of the fifo, to ensure that the rearranged order is preserved.

Increased performance of graphics memory using page sorting fifos

A memory controller for use in a graphics system includes a dual-pipeline architecture that maximizes the utilization of a dual-banked graphics memory. The dual-pipeline architecture allows for accesses for each bank to be forwarded separately within the memory controller prior to transferring them to the dual-banked graphics memory. Processing hardware is shared between the pipelines of the memory controller to minimize hardware overhead. By grouping access according to the bank with which they are associated, an arbitrator of the memory controller can provide data references to a frame buffer memory in a more desirable order. In addition, the delays associated with accessing a bank may be minimized, since the bank addresses are available at both pipeline outputs before they require processing. Thus, while one bank is being accessed, preparations for accessing the second bank may be initiated.

Dual-pipeline architecture for enhancing the performance of graphics

A frame buffer cache includes a dual-input, dual-output storage cell to multiplex frame buffer tile data and pixel data. Tile data stored in one format while pixel data is stored in a second format. The cache allows for buffering the data in the two different formats so as to provide the data in the format as needed. Pixel data is retrieved from the tile data and file data is retrieved from the pixel data. The storage cell includes a multiple-bit latch and tri-state buffers which connect each storage cell to a tile data bus and a pixel data bus. A number of bus lines and components are reduced due to the use of the tri-state buffers.

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Fort Collins, CO, United States of America

James A Schinnerer