Sun Microsystems, Inc.

James A Mott

Elisa Rodrigues

David J Redman

William M Baldwin

Ashish Munjal

Nancy Lee

Arvind Kini

A system and method for tracking responses to InfiniBand RDMA Reads. When an RDMA Read or Read request is issued by a transmit module, a receive module is informed of the packet sequence numbers (PSN) associated with the expected RDMA Read responses. The receive module maintains a linked list for each queue pair that issues RDMA Reads. Each entry in the linked list corresponds to one RDMA Read for the associated queue pair, and identifies the first and last PSN and includes a link to the next entry in the linked list. When the final RDMA Read response is received, the receive module notifies the transmit module, which can then retire the RDMA Read from its retry queue.

System and method for tracking infiniband RDMA read responses

A system and method for implementing flow control, at the link and/or transport layers, for InfiniBand receive traffic. A shared memory structure may be used for combined queuing of virtual lane and queue pair traffic. Each virtual lane is allocated a number of memory buffers; a packet is dropped if buffering it would cause its virtual lane to exceed its allocation of buffers. For each active queue pair, a linked list of buffers is maintained in the structure. Each queue pair is dedicated zero or more of its virtual lane's buffers, and may also use a set of buffers shared among multiple queue pairs. Thresholds are established in a queue pair's dedicated set of buffers and/or the shared set of buffers. As each threshold number of buffers is used, a queue pair can advertise fewer message credits. RNR-NAKs are issued when no more buffers are available to a queue pair.

System and method for infiniband receive flow control with combined buffering of virtual lanes and queue pairs

A system and method for mapping outbound communications (e.g., encapsulated Ethernet packets) from InfiniBand queue pairs (QP) and/or virtual lanes (VL) to ports through which they are to be transmitted to an external communication system. A memory is shared between the InfiniBand receive side and transmit side. A shared control structure facilitates management of a linked list for each queue pair. A linked list is composed of entries in the control structure; each entry stores a value identifying the next control entry in the list and a memory bucket associated with the entry. Each queue pair terminating has a head pointer identifying the first control entry and memory bucket, and a tail pointer identifying the last control entry and memory bucket of a linked list. When a communication is reassembled, pointers defining a sub-list comprising the communication are passed to a network transmit module.

System and method for mapping InfiniBand communications to an external port, with combined buffering of virtual lanes and queue pairs

A system and method for processing interleaved Sends of encapsulated communications and responses to RDMA Reads in a single InfiniBand queue pair receive queue. The queue is implemented as one or more linked lists of memory buckets, and stores Send commands (containing encapsulated communications or RDMA Read descriptors for retrieving a communication) until their associated communications are assembled and forwarded to a transmit module. The queue grows as new InfiniBand packets are received, and shrinks as communications (e.g., Ethernet packets) are forwarded. A next packet pointer identifies the next Send command whose communication should be assembled. If it is an encapsulated communication, the communication is forwarded. Otherwise, RDMA Read requests are issued and the responses bypass the tail of the queue and are assembled in an assembly area at the head of the queue.

System and method for interleaving infiniband sends and RDMA read responses in a single receive queue

A system and method for shared buffering of InfiniBand virtual lanes and queue pairs. Instead of allocating dedicated memory space (e.g., a set of FIFO queues), a shared memory dynamically accommodates traffic received on different virtual lanes and/or queue pairs of an InfiniBand network. A multi-port RAM comprises memory buckets or elements for storing contents of InfiniBand packets. For each queue pair and/or virtual lane, matching head and tail pointers identify the first and last elements of a linked list of traffic buffered from that queue pair or virtual lane. A multi-port control structure mirrors the RAM. For each node in a queue pair or virtual lane's linked list, a corresponding entry in the control structure relates to the corresponding memory element and stores an identifier of the memory element and control entry corresponding to the next node in the linked list.

Combined buffering of infiniband virtual lanes and queue pairs

A system and method for providing dynamic rate flow control. An originating entity sets requested and target rates of communication within a communication sent to a destination entity. The requested and target rates may be expressed in terms of a 'time to next communication' (e.g., a period of delay between transmission of successive communications). Intermediate devices (e.g., switches, routers) may decrease a target rate (thereby increasing the time between communications) but not the requested rate. Through a feedback process, the destination entity (or an intermediate entity) reports the target rate, and possibly the requested rate, back to the originator, which may accept and implement a reduced rate of communication, select a different communication channel, etc.

System and method for dynamic rate flow control

An apparatus and method for enabling hot swapped circuit boards to receive multiple power voltages from a backplane and supply the multiple power voltages to devices on the circuit board in a predictable sequence. An apparatus according to the invention would include a circuit board having an electrical connector, a sequencing circuit, and an element. The electrical connector of the circuit board receives the multiple power voltages from another circuit board, such as a backplane or motherboard. The sequencing circuit receives the multiple power voltages from the electrical connector. When a part of the sequencing circuit receives a signal indicating that the sequencing circuit has received a first power voltage, the sequencing circuit provides a second power voltage to the element electrically coupled to the sequencing circuit.

System for supplying multiple voltages to devices on circuit board through a sequencing in a predictable sequence

A system and method for providing hot swap capability with minimal changes in a system which uses existing circuitry and drivers. In one embodiment, a computer system has a host processor and a hot-swap-capable device, each coupled to a Compact PCI bus. The device includes one or more pre-existing circuits (ASICs and/or standard off-the-shelf circuits) and corresponding pre-existing drivers. A hot-swap-capable bus bridge is interposed between the circuits and the Compact PCI bus to provide hot swap functionality while allowing the pre-existing circuits and drivers to be used without modification. In one embodiment, an Intel 21554 is used as the hot-swap-capable bus bridge. The 21554 is programmed to emulate a transparent bridge. Modified drivers in the OBP firmware and OS software allow the system to recognize the 21554 in this transparent configuration and to probe the secondary side of the 21554 for the circuits.

System and method for providing hot swap capability using existing circuits and drivers with minimal changes

An apparatus and method for comparing identifications of circuit boards in a midplane. When a first circuit board and a second circuit board are inserted into opposite sides of the midplane, an incompatibility between the first circuit board and the second circuit board may damage or impair the operation of one or both of the first circuit board and the second circuit board. To solve this problem, a first identification is stored on the first circuit board and a second identification is stored on the second circuit board. If the first identification of the first circuit board and the second identification of the second circuit board indicate an incompatibility, then one or both of the first circuit board and the second circuit board is/are prevented from fully powering up.

Growing community of inventors

Oakland, CA, United States of America

James A Mott