International Business Machines Corporation

James A McDonald

Michael F McAllister

Madhavan Swaminathan

Gordon J Robbins

Keshav B Prasad

Eric D Perfecto

Chandrika Prasad

George E White

Gregory Martine Wilkins

Thomas J Walsh

Arthur Bross

Robert O Lussow

Clive Allan Collins

Donald E Myers

Julian G Cempa

Thomas J Walsh, Iii

Joseph D Peruffo

A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.

Method of constructing an integrated circuit memory

A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Method for repairing defective electrical connections on multi-layer

High density memory structure

A thin-film arrangement for a non-planar structure is described. The structure includes a substrate and a plurality of thin-film layers stacked on top of each other above the substrate. The layers contain conductive patterns and vias that provide connections between the conductive pattern in one of the layers to the conductive pattern in another layer. Vias that provide a connection between the conductive pattern of one layer to the conductive pattern in another remotely located layer are offset and in contact with respect to each other and are positioned in a non-linear arrangement, preferably in the form of a helix or a multiple helix.

Thin-film wiring layout for a non-planar thin-film structure

A method is provided for forming one or more electrical conductors in a multilayer structure such as a computer component during a punching operation. A conducting sheet is placed in direct contact with a sheet of a deformable dielectric material. A punch is used to form a conducting slug from the sheet and to simultaneously transfer the slug into the dielectric material. During the transfer operation, a portion of the dielectric material is displaced so as to cause a mechanical interference between the slug and dielectric material.

Method of direct transferring of electrically conductive elements into a

A carrier module such as a chip carrier or a circuit board has a matrix of programmable connection pads for attaching a VHDLSI chip. Each pad is encircled by circuit elements (lines or vias) providing different power or signals and one of the lines or vias is selectively connected to the pad to program the connection. The pads have cut outs at the connection points to the vias and/or lines in order to simplify making of connections. The programming connections between the vias and/or lines and the pads are made after pre-finishing the board by depositing evaporated metal to form a bridge between each pad and a via or line selected for each pad. Then a passivation layer of polyimide is deposited on the vias and/or lines with an aperture at the center of each pads so that solder connections to attach the chip to the carrier module do not erroneously bridge to additional vias and/or lines.

Programmable chip to circuit board connection

A high performance computer system package integrates the switches and memory in the core of the package with the processors distributed about the periphery of this core. The request and response switches and the input or output lines are on platters and storage modules are coupled between the platters.

High performance computer system with platters and unidirectional

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Newburgh, NY, United States of America

James A McDonald