General Electric Company

James A Loughran

Douglas E Houston

Thomas R Anthony

Alexander J Yerman

Dominic A Cusano

Homer H Glascock, Ii

Constantine A Neugebauer

Harold F Webster

Yen Sheng Sun

James F Burgess

Richard O Carlson

James G McMullen

Multilayer circuit boards composed primarily of silicon and containing buried ground planes and buried conducting runs are fabricated in one embodiment by positioning conductive patterns (12) on the surfaces of silicon substrates and melting a solder component of the conductive patterns (12) and allowing it to flow together with solder from the conductive patterns (12) on a stacked, adjacent silicon substrate (10). When the solder cools, a single conductive pathway (18) exists between adjacent silicon substrates (10) and bonds the adjacent substrates. If the substrates are coated with SiO.sub.2 (20), a multilayer structure with buried microwave strip lines (22) is formed in the bonding process. Alternatively, highly resistive silicon substrates (26) are used as a dielectric for microwave strip lines (24) on a top surface thereof and a conductive sheet (28) on the bottom surface thereof acts as a ground plane for microwave energy propagating along strip line (24).

Multilayer circuit board fabricated from silicon

A method for producing a hole in a polymer film includes the steps of depositing a conductive layer onto the polymer film and irradiating a spot on the layer with a burst of focused laser energy at a level sufficient to form an opening in the film and, subsequently, plasma etching the film so as to form a hole of desired depth in the polymer film underlying the opening in the conductive layer. This method is particularly applicable to the formation of multichip intergrated circuit packages in which a plurality of chips formed in a semiconductor wafer are coated with a polymer film covering the chips and the substrates. The holes are provided for the purpose of interconnecting selected chip contact pads via a deposited conductive layer which overlies the film and fills the holes.

Method for producing via holes in polymer dielectrics

A method for depositing gold bumps on metallized pads of semiconductor chips uses a commercially available thermocompression or thermosonic gold wire bonder. The method includes the steps of depositing a gold ball with an attached wire on the metallized pad, and removing the wire so that a gold bump remains on the pad.

Method of fabricating gold bumps on IC's and power chips

A semiconductor device and a method for its preparation are disclosed, wherein a body of semiconducting material has at least one bore extending completely therethrough, this bore having a substantially constant diameter of less than about 1.5 mils and an average length-to-diameter ratio of at least about 6:1, this bore being defined by a region of the semiconducting material in the recrystallized state having therein throughout the region a substantially constant uniform concentration level of atoms of at least one metal selected from the group consisting of aluminum, indium, gallium, antimony, gold, silver and tin in addition to the initial content of the semiconducting material.

Method for producing high-aspect ratio hollow diffused regions in a

Power semiconductor devices are manufactured using a flexible metal tape carrier to facilitate automation of the manufacturing process. Control leads are fashioned from portions of the tape carrier, with a main portion of the tape carrier serving as a main current lead. The manufacturing process permits thorough electrical testing of a power semiconductor chip prior to incorporation into a relatively expensive power device package. In particular, the power chip can be tested at full-rated current, at least where the current is pulsed at a low duty cycle.

Tape automated manufacture of power semiconductor devices

A semiconductor device and a method for its preparation are disclosed, wherein a semiconductor body has at least one bore extending completely or partially therethrough, this bore being defined by a semiconducting region having a conductivity type opposite to, and resistivity lower than, the material of the body contiguous to the bore-defining semiconducting region, this bore having a substantially constant diameter of less than about 1.5 mils and an average length-to-diameter ratio of at least about 6:1.

High-aspect-ratio hollow diffused regions in a semiconductor body

A silicon circuit board incorporates multiple levels of patterned conductors. First level upper and lower patterned conductors are situated on an insulation-coated, monocrystalline silicon substrate. Upper and lower, high resistivity, polycrystalline silicon layers, in turn, are situated on the first level upper and lower patterned conductors, respectively. Second level upper and lower patterned conductors are situated over the upper and lower polycrystalline silicon layers. Further levels of patterned conductors in the circuit board may be provided by iteratively forming on the board polycrystalline silicon layers and patterned conductors. Conducting feedthroughs in the circuit board provide electrical communication between various patterened conductors.

Low loss, multilevel silicon circuit board

A semiconductor device for the detection of radiation in general and X-radiation and infrared radiation in particular is provided.

Drilled, diffused radiation detector

An improved method for thermo-compression diffusion bonding allows bonding of a compliant metallic member to a second metallic member which may have surface irregularities. Opposite surfaces of the compliant metallic member are contacted by a layer of compactible material and by the second metallic member, respectively, such that distribution of a loading force applied to this assembly conforms the compliant member to the irregularities in the surface contour of the second metallic member. Thus, a uniform substantially void-free diffusion bond between the two metallic members is achieved.

Method for thermo-compression diffusion bonding

Disclosed is a double side cooled, pressure mounted semiconductor package and a method for the manufacture thereof. The package is formed by directly bonding upper and lower metal contact assemblies to an annular ceramic housing. Assembly is simplified if at least one contact assembly comprises two parts applied sequentially. An annular flange having a central opening approximately the size of the central opening in the annular housing and having an outside diameter larger than the outside diameter of the ceramic housing is direct bonded to one end of the housing simultaneously with a lower semiconductor contact. After a conventional semiconductor pellet is positioned in the housing, the second part, a metal contact disc with an outside diameter approximately equaling the outside diameter of the flange, is positioned thereover. Finally, the flange and the disc are welded around their peripheries.

Double side cooled, pressure mounted semiconductor package and process

Disclosed is a method of bonding metals to substrates such as ceramics or metals. A bonding agent forms a eutectic alloy with the metal to provide bonding. Several methods of supplying the bonding agent to the system are disclosed. However, regardless of which method of introducing the bonding agent into the system is employed, the quantity of the bonding agent is carefully controlled so that the compound in the region of the bond is hypoeutectic. To form the bond, the metal and the substrate are placed adjacent each other and the bonding agent is introduced into the system. The system is then heated to a temperature between the eutectic temperature and the melting point of the metal for a preselected time. The system is then cooled to form a bond. The heating is carried out in an inert atmosphere or a vacuum.

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Scotia, NY, United States of America

James A Loughran