Creative Integrated Systems, Inc.

Rocoh Company, Ltd.

Hycom Incorporated

Creative Integrated Ststems, Inc.

James A Komarek

Clarence W Padgett

Jack L Minney

Scott B Tanner

John F Stockman

Harold F Lewis

Stephen P Nordine

Richard Wada

Keiji Fukumura

Motohiro Oishi

Shin-ichi Kojima

H Nakanishi

Robert D Amneus

A circuit attenuates echo caused by line variations and a transformerless, high DC impedance, two-wire line interface. To reduce echo, a test tone is introduced on the communication line with all station units connected to the line. The resultant receive signal is conditioned through a peak detector, digitized and read by a processor. The resistive and capacitive characteristics of a network are iterated by the processor and the results remeasured. The network is set to the best combination for least echo by the processor. An interfacing system capacitively couples a plurality of sources to a two-wire communication pair by means of a plurality of differential voltage-to-current amplifiers. Each source uses a differential receiving amplifier to receive signals from the line and is resistively coupled in parallel to all the sourcing entities coupled to the communication line at that particular interface. There is an echo balance network associated with each source.

Circuit for attenuation of echos caused by line variations and an interfacing system for capacitively coupling a plurality of sources to a two-wire communication line

A small and economically fabricated CMOS voltage controlled crystal oscillator is provided by coupling three inverter amplifiers in series with a regenerative crystal controlled feedback loop. The first and second CMOS inverters have output nodes whose impedances are modified by a CMOS impedance modulating circuit. Also coupled to each of these two output nodes is a CMOS transistor shunt capacitor. The impedance of the output node is modified according to the magnitude of a voltage control signal applied to the CMOS modulating circuits. The self-bias of the modulating circuits is maintained substantially constant by adjusting the gate drive in each of the modulating circuits according to gate drives derived from a dummy modulating circuit. The dummy modulating circuit has as one input the voltage control signal and as its compensating gate drive, a control signal derived from a feedback loop from a dummy output node in such a manner that the self-bias of the dummy modulating circuit is maintained substantially constant. The compensating gate drive from the dummy modulating circuit is then coupled to the appropriate compensating gates within the impedance modulating circuits in the voltage controlled oscillator.

Home and small business phone system for operation on a single internal

An input receiver circuit in a read-only memory is provided with a feedback to control hysteresis. A second stage and an additional output is added to the receiver. Switching circuit noise from inside of the read-only memory is isolated by the added state and outputs, and cannot be fed back into the receiver circuit to affect the detection of the TTL voltage levels. Use of wide and long FET sizes minimizes the manufacture related variations in the input receiver switching levels.

NMOS input receiver circuit

A low power, low noise driving circuit for a bank of LEDs utilized in the station units of the MAN system is provided by coupling each bank of LEDs in a series circuit between the voltage supply and a constant current source. Each LED has a controllable logic switch in parallel across it and the switches are further in series circuit with each other to form a ladder network. Any selected LED may be turned off by closing its corresponding logic switch. The current continues to flow then through the shunting switch into the remaining LEDs in the series circuit that are on. A plurality of such ladder networks may be coupled in parallel with each other and each ladder network controlled by a switching gate which selectively couples it to the constant current source so that the LED ladder networks are operated at a predetermined duty cycle. Current spikes are avoided across the voltage supply by driving the connecting control gates in an overlapping relationship so that the constant current source is never disconnected from the voltage supply.

Incremental values of a plurality of capacitors are programmably coupled through ROM core FETs with selective threshold voltages, EPROM core FETs, RAM cells, ROM fuse links or antifuse ROM links to a dummy bit line. The dummy bit line carries a bit line voltage to simulate either the worst case logical one or worst case logical zero within a read-only memory array of memory cells. The dummy bit line voltage is used as a control signal to a trigger circuit. The trigger circuit generates at the appropriate threshold a triggering signal used to control sense amplifiers coupled to the memory circuit. Therefore, by programmably altering the delay time on the dummy bit line, the read cycle of the memory can be programmably altered to either minimize the read time cycle to provide a fast, high quality memory product, or to maximize the read time cycle to provide for a slower but higher yield memory product at less expense.

Memory circuit yield generator and timing adjustor

A memory precharge voltage, VPC, is provided which tracks changes in the high voltage supply, VDD, according to a measured degree, which maintains a precharge voltage notwithstanding transient loads which may tend to draw the precharge voltage down, and which maintains the precharge voltage at the operating level notwithstanding the fact that the precharge generator is substantially turned off during a power down condition. The precharge voltage, VPC, is then used as the controlling input signal to a circuit which it generates and an internal control voltage, MLC, used to drive small pull-up current FETs coupled to the bit lines in the ROM core. The internal control signal MLC is generated to track the discharge current in a bit line within the memory core, to track VPC, and to be maintained at its operating voltage level even when the MLC current is substantially turned off during a power down condition.

VLSI memory circuit

The invention is a telephone system capable of operating on a single internal telephone line as commonly found in the home or small businesses, which is economically implemented within an integrated circuit chip to provide a one chip telephone and which provides most of the components necessary for a full-featured, reliable and easy to install office communication system. The multiband audio network (MAN) transfers four audio bands and a digital data band over a single twisted pair of wire. A 6,000 bits per second full duplex digital data channel is also provided on the same twisted pair. Each station unit includes all the control and interface support necessary to perform conventional telephone functions. These functions include a combination of keyboard and display support circuitry such as strobe and debounce circuitry, LED buffers, piezo ring drivers, control registers and communication hardware. Everything needed to provide a programmably customized communication and telephone network is available using only one basic chip design in the system as described above. Not only are standard telephone communications possible on a single twisted pair, but a network of telephone receivers, computers, modems, telefax devices, answering machines and any other type of information handling or communication device now known or later devised for use on a telephone line can be networked and accommodated within the system.

The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines in the memory array are precharged to ground during the precharge phase. Next, during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line at ground and switch the second virtual ground line to a positive voltage. All bit lines are precharged to ground during the precharge phase. In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage. If the selected memory core FET is programmed with a high threshold voltage, the bit line remains floating at the ground level, or it may be held at ground by means of the second virtual ground line, which is held at ground, and by low threshold core FETs, adjacent to the selected core FET, which are connected to the selected word line. The total diffusion capacitance on a virtual ground line is minimized when the memory cells connected to the line are programmed with more logic zeros than logic ones.

Driver circuit for addressing core memory and a method for the same

The address transition detection circuit is improved by holding the previously latched address signal until a predetermined delay after receipt of the new address signal.

Semiconductor read-only VLSI memory

An improved precharge timing control is provided by turning off the first one of a series of precharge clocks PC0 by means of discharging a single dummy word line. The dummy word line is comprised of a plurality of dummy word line segments wherein each of the segments are charged in parallel, but discharged in series. The discharge time required of the plurality of word line segments is sufficient to allow discharge of an end of a selected word line in the read only memory to ground. Improved timing with good performance is achieved by turning off the earliest precharge clock PC0 among a series of precharge clocks PC0 and PC1, for example, so that an improved precharge time for the ROM core for a fast process parameter is realized.

Very large scale integrated planar read only memory

The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by a number of different improvements in various circuits and methodologies utilized in the memory. One of the improvements relates to control of an output buffer by a control circuit. The output enable signal to the output buffer is selectively inhibited by the control circuit which determines when the memory cycle is actually completed. Only after the memory cycle is actually completed is the conventional chip enable signal, CE, coupled to the enable input in the output buffer.

The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an output enable latch circuit which provides internal memory signal of whether the memory was operating in the standby or active mode during a previous memory cycle and a data latch circuit which provides an internal memory signal of whether a new read cycle is beginning within the memory. The data latch circuit is reset when address detection has occurred within the memory. A logic circuit combines an output of the data latch circuit, which is indicative of a memory read cycle, with an output of the output enable latch circuit, which is indicative of whether the prior memory cycle was standby or active. The logic circuit generates an output enable signal, OE, which is coupled to the output drivers of the memory to control float of the output drivers. As a result, a smooth transition from old data to new data is obtained, and system data bus contention in transitions from standby to active modes is eliminated.

Output driver control for ROM and RAM devices

Operation of an address latch circuit in a memory is conditioned on first receiving a ground surge control logic signal, SURG, which is generated only when data output drivers switch. This prevents noise from these same drivers from falsely addressing the memory. Metastability is prevented by selecting the trigger points of the gates which make up the latch such that an output is not generated until input or intermediate circuitry has stabilized and by providing a favored output condition in the input or intermediate circuitry when conflict between almost simultaneous inputs occur. Feedback of the output of the latch to its input further reduces metastability.

A circuit which differentially amplifies voltages that are close to ground with differences of about 0.15 volts uses voltage level shifters, a cross coupled current source and inverters to provide increased speed, accuracy, and gain. Symmetric cross coupled current sources are used in a differential amplifier to provide the differential amplifier with a balanced load. A symmetric and balanced layout senses smaller voltage differences and operates faster than would otherwise be possible. The gain of the cross coupled current source is controlled by four FETs. Voltage level shifters at the input to the differential amplifier allow the differential amplifier to sense signals that are close to ground with a voltage difference of about 0.15 volts. The voltage level shifters also shift the signals to a voltage that increases the gain of the differential amplifier. Two inverters block half level signals from being outputted until the sense amplifier data has been latched. By blocking half level outputs of the differential amplifier, a race condition is eliminated and output enable signal, OE, which may then switch sooner than would otherwise be possible.

Improvemetns in a detection circuit with a level shifting circuit

The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.

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Newport Beach, CA, United States of America

James A Komarek