United States of America As Represented by the Secretary of the Air Force

Sperry Corporation

Printware, Inc.

James A Howe

Donald V Mager

Katherine A Splett

John H Andreasen

A photosensitive, photoconductive media moving in a first direction relative to a laser light beam scanning in a second direction, transverse to the first direction, incurs velocity variations. These velocity variations result in variations in the absolute and relative heights of white and black image features. This printed image nonuniformity is especially visually detectable for closely spaced parallel lines in the second direction, and/or gray scale. An optical velocity sensor senses instantaneous media velocity. An analog or digital velocity error processor maintains a running average velocity and determines, by subtraction, an instantaneous velocity error as the difference between currently sensed and running average velocities. The instantaneous velocity error so determined is used to adjust the intensity of the laser light beam to be proportionally brighter (dimmer), exposing a wider (narrower) scan line, on a faster-moving (slower-moving) media region. By this compensating, the ratio of white and black image features is maintained constant during media velocity variations.

Modulating laser intensity in a laser printer proportionately to the

A synchronous clock circuit is provided on each module of an electronic digital system formed of a plurality of modules. Each clock circuit has two control pins which are used by control logic to determine whether or not the clock on a particular module is disabled, is operating as the master clock for the system, or is providing a backup function for the master clock. The common clock line is supplied through a buffer to the components on the module which require clocking. Logic circuitry on the backup clock mode insures the backup clock is in a ready condition in case there should be either failure of the master clock oscillator or if the master clock module is removed from the unit. All of the clock circuits of the different modules may be constructed in an identical manner, with the control of the function of the circuitry being provided simply by control of the logic level on the two terminals. A clock detecting time-out circuit is provided on each of the modules, which has a timing period which is slightly longer than the clock period. If the master clock fails to produce a clock pulse at the time that it should, the clock detect timing circuit, which is coupled to the buffer of the backup module, will sense that a failure has occurred and will control the turn-on of the clock circuit for the backup module.

Redundant synchronous clock system

A dynamic damping apparatus wherein the current source is critically damped during rise and fall of current but the DC flattop of the current is unaffected by the fluctuations of load voltage. Therefore the output impedance of the current source is low during rise and fall times, but high during the flattop. This increases current source regulation.

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Burnsville, MN, United States of America

James A Howe