Quantum Corporation

Maxtor Corporation

James A Henson

William R Akin, Jr

Richard M Ehrlich

Ara Patapoutian

Kevin Dean Fisher

Michael D Leis

Clifford M Gold

Mathew Power Vea

Gregory R Kahlert

Minnie T Uppuluri

Horia Cristian Simionescu

Bruce R Peterson

Christopher Montgomery Carpenter

Scott E Richmond

Tim R Glassburn

James H Do

James P McGrath

Michael L Raab

Nathan J Hays

Parminder Gill

Lance D Beazley

Luan Kha Bui

A single microprocessor ( ) hard disk drive ( ) having a shared buffer memory ( ) for storing sector data as well as microprocessor variables and code includes a buffer manager ( ) for arbitrating requests from various channels or clients for access to the shared buffer memory. The buffer manager arranges channels including a disk data channel ( ), a host interface channel ( ), and microprocessor channels ( ) into a round-robin circular priority queue, with the disk data channel normally assigned the highest priority for buffer access. A state machine carries out an arbitration cycle by sequentially servicing access requests pending within the queue. The state machine senses ( ) a servo interrupt (SVOINT) to elevate the priority of any pending microprocessor access requests to the shared buffer, such that the requests are serviced and cleared rapidly to allow the servo interrupt servicing routine to start sooner. The servo interrupt is preferably asserted during a spoke gate ( ) time when a head ( ) is sensing a disk ( ) servo region (S). During this time data transfers between the disk and the shared buffer memory are stopped, pending buffer memory data transfers can be paused, and head seeking and tracking is controlled. This technique reduces the uncertainty delay in starting the servo interrupt service routine by 10 percent, which restores otherwise lost processing time and reduces head positioner servo ( ) phase jitter, thereby improving head tracking and seeking performance.

Method of arbitrating requests for access to a single buffer memory in a disk drive

A magnetic disk drive data storage disk defines recording tracks divided into data sectors by narrow servo spokes. A data sector lying between servo spokes is recorded with user data encoded in accordance with a code having a predetermined distance and user data code rate. Each servo spoke of the recording area has at least one servo information field encoded in a wide bi-phase code pattern. The disk drive further includes a synchronous sampling data detection channel having a data transducer head positioned by a servo-controlled actuator over the recording track, a preamplifier for receiving electrical analog signals magnetically induced by the data transducer head from flux transitions present in at least the servo information field, a digital sampler for synchronously sampling the electrical analog signals to produce digital samples, and wide bi-phase decoding circuitry coupled to receive digital samples from the synchronous sampling data detection channel for decoding the wide bi-phase code pattern.

Synchronous detection of wide bi-phase coded servo information for disk drive

Interrupt signal prioritized shared buffer memory access system and method

A method and apparatus for arbitrating requests for access to a single buffer memory embedded within a disk drive in which a disk data channel is assigned a highest priority for buffer access within a queue. An arbitration cycle progressively services access requests pending within the queue, beginning with providing buffer access to the disk data channel and following with accesses to other channels during an arbitration cycle completion interval in accordance with a round-robin circular priority arrangement providing orderly access to all channels contending for memory access. At the end of completion interval, buffer access returns to the disk data channel, and thereafter, the arbitration cycle is repeated.

Time allocation shared memory arbitration for disk drive controller

A method for managing data blocks in a cache buffer defining date block segments, and for automatically transferring data into and out of the cache buffer. A cache list comprises a plurality of entries each including information identifying a corresponding cache segment, and a set of consecutive data blocks stored in the cache segment. Providing cache status for a requested set of date blocks includes traversing the cache list to locate entries identifying the starting data block in the requested set, and consecutive data blocks successively following the starting data block without interruption, and identifying as a missing data block the first data block in said succession, including said starting data block, not identified in any entry. The missing data block is used to provide status: a full hit if the missing data block is not in the requested set; a miss if the missing data block is the starting data block in the requested set, or a partial hit otherwise. In response to a write command for a new set of data, the cache list is traversed to locate all entries identifying sets of data blocks overlapping the new set. If a located entry identifies a set of data blocks fully overlapping the new set, there is a full hit. If no entry is located, there is miss. Otherwise, there is a partial hit. The new set can be automatically transferred into a predesignated buffer area selected by the cache manager.

Embedded cache manager

Synchronous detection of wide bi-phase coded servo information for disk

A method of holographic recording in a photorefractive medium wherein stored holograms may be retrieved with maximum signal-to noise ratio (SNR) is disclosed. A plurality of servo blocks containing position feedback information is recorded in the crystal and made non-erasable by heating the crystal. The servo blocks are recorded at specific increments, either angular or frequency, depending whether wavelength or angular multiplexing is applied, and each servo block is defined by one of five patterns. Data pages are then recorded at positions or wavelengths enabling each data page to be subsequently reconstructed with servo patterns which provide position feedback information. The method of recording data pages and servo blocks is consistent with conventional practices. In addition, the recording system also includes components (e.g. voice coil motor) which respond to position feedback information and adjust the angular position of the reference angle of a reference beam to maximize SNR by reducing crosstalk, thereby improving storage capacity.

Position feedback system for volume holographic storage media

A clock generation circuit includes a reference clock for putting out a stable reference clocking signal. A digital ring oscillator includes a series circuit loop having at least one inverting gate and a programmable delay line of plural delays formed a series of tapped digital transmission gates connected between an output and an input of the inverting gate. A multiplexer selects among the series of taps in accordance with a tap selection signal. A clock monitoring circuit is connected to compare the clock output with a stable reference clocking signal to produce a digital clock cycle count. A programmed microcontroller generates the tap selection value as a function of the digital clock cycle count and a desired clock output frequency set point. And, a synchronization circuit synchronizes tap selection value applied to the multiplexer in relation to the present, adjustable clocking signal, and to a logical state of a successor, adjustable clocking signal to be put out by the digital ring oscillator following the tap selection, in order to avoid glitches and without interrupting oscillation.

Glitchless frequency-adjustable ring oscillator

An improved disk drive architecture includes a microcontroller interface circuit connected between a drive microcontroller and a buffer controller. The microcontroller interface circuit includes address mapping registers for mapping at least one predetermined portion of directly addressable memory of the microcontroller to address locations of the drive's cache buffer. The buffer controller circuit includes an access arbitration circuit for arbitrating requests for access to the cache buffer by the drive's data sequencer, the drive's host interface controller and the drive's microcontroller. A microcontroller wait state generator responds to the access arbitration circuit by generating and applying a wait state sequence to the microcontroller until a request it makes for access to the cache buffer can be executed.

Shared memory array for data block and control program storage in disk

Growing community of inventors

Morgan Hill, CA, United States of America

James A Henson