Bell Telephone Laboratories

At&t Bell Laboratories

Other

American Telephone & Telegraph Co., At&t Bell Laboratories

James A Davis

Peter W Shackle

William F MacPherson

Thomas L Hiller

Harry E Mussman

Mark W Beckner

William J Ooms

Gilbert A Van Dine

Philip D Olson

Eric J Gausmann

Douglas A Spencer

Rolfe E Buhrke

A method and apparatus for decreasing delay and use of data processing resources in the reliable transmission of data frames in a packet network. In transmitting data from a source to a destination over a plurality of intermediate data switching points, the data processing required for each frame is selectively varied at each data switching point, according to the requirements for transmission of data frames of a message and of the succeeding link used for that message. A virtual link address is transmitted with each data frame which is translated into the mode of processing the frame at the data switching point, and into the virtual and real address of the next data link. Advantageously, such an arrangement allows for minimizing the data processing load and delay at each protocol handler of the data path through the packet network.

Fast packetized data delivery for digital networks

To switch a first gated diode switch (GDSL1) to the 'OFF' state requires a voltage applied to the gate which is more positive than that of the anode or cathode and a sourcing of current into the gate of substantially the same order of magnitude as flows between the anode and cathode of the first switch. Control circuitry, which uses a second gated diode switch (GDSC) coupled by the cathode to the gate of the first switch (GDSL1), is used to control the state of the first switch (GDSL1). The control circuitry also comprises a first branch circuit coupled to the anode of the GDSC and to a first potential source V1 and a second branch circuit coupled to the anode of GDSC and to a second potential source V2 which is of a lower potential than V1. The second branch circuit has a high voltage and high current capability switch in series between V2 and the anode of GDSC. The first branch circuit has a high voltage but modest current handling switch in series between V1 and the anode of GDSC. The second branch circuit is used to provide a surge of current if and when needed during the current break operation to turn GDSL1 to an OFF state and the first branch circuit is used to maintain the state of the load switch. The second branch circuit can be shared by many control circuits.

Control circuitry using two branch circuits for high voltage solid-state

An integrated packet switching and circuit switching system comprising a number of switching modules each connected to a corresponding plurality of user terminals. Each switching module includes a time-slot interchange unit for providing circuit-switched communication channels and a control unit that controls the operation of the time-slot interchange unit. Each switching module also includes a packet switching unit used both to provide packet-switched communication channels among the user terminals connected to that switching module, and to switch control information between the user terminals and the control unit to establish circuit-switched calls and packet-switched calls. A time-multiplexed switch interconnects the switching modules to provide circuit-switched communication channels and packet-switched communication channels between user terminals of different switching modules.

Distributed packet switching arrangement

An integrated packet switching and circuit switching system comprising a number of switching modules each connected to a different plurality of user terminals. Each switching module includes a time-slot interchange unit for providing circuit-switched communication channels and a control unit that controls the operation of the time-slot interchange unit. Each switching module also includes a packet switching unit used both to provide packet-switched communication channels among the user terminals connected to that switching module, and to switch control information between the user terminals and the control unit to establish circuit-switched calls and packet-switched calls.

Integrated packet switching and circuit switching system

To switch a first gated diode switch (GDS1) to the 'OFF' state requires a voltage applied to the gate which is more positive than that of the anode or cathode and a sourcing of current into the gate of substantially the same order of magnitude as flows between the anode and cathode of the first switch. Control circuitry, which uses a second gated diode switch (GDSC) coupled by the cathode to the gate of the first switch (GDS1), is used to control the state of the first switch (GDS1). The control circuitry comprises a first branch circuit coupled to the gate of GDSC and to a first potential source +V1, a second branch circuit coupled to the anode of GDSC and to a second potential source +V2, and a third branch circuit coupled to the anode of GDSC and to a third potential source +V3. The first branch circuit is connected to the gate of the second switch (GDSC) and controls the state thereof. The second branch circuit maintains the state of the load switch (GDS1) and is adapted to supply up to a preselected maximum amount of current into the anode of GDSC and then to automatically reduce the amount of supplied current substantially. The third branch circuit is used to provide a surge of current during a current break operation to turn GDS1 to an OFF state.

Control circuitry for high voltage solid-state switches

To switch a first gated diode switch (GDS) to the 'OFF' state requires a voltage applied to the gate which is more positive than that of the anode or cathode and the sourcing of current into the gate which is of the same order of magnitude as flows between the anode and cathode. Control circuitry, which uses a second GDS coupled by the cathode to the gate of the first GDS, is used to control the state of the first GDS. The state of the second GDS is controlled by a branch circuit having a relatively modest current handling capability. An n-p-n junction transistor has the emitter and collector coupled to the cathode and gate, respectively, of the first GDS, and has the base coupled through a p-n-p transistor to the input terminal of the control circuitry. The n-p-n transistor facilitates a quick turn-on of the first GDS by rapidly bringing the potentials of the gate and cathode of the first GDS to levels which are close together.

Control circuitry using a pull-down transistor for high voltage field

A bilateral solid-state crosspoint for use in a telecommunications switching network is disclosed comprising a pair of Darlington connected pairs of transistors connected in a complementary relationship. The transmission path in each direction through the crosspoint comprises a Darlington connected pair of transistors and one additional semiconductor junction. A control circuit provides base drive to the transistors to close the crosspoint.

Rugged crosspoints for communication systems

Symmetrical integrated transistors and drive circuitry provide low loss bilateral analog crosspoints for a switching matrix. Each crosspoint comprises a high performance PNP lateral transmission switching transistor and an associated NPN vertical drive transistor formed over a common n-type buried tub in a p-type substrate. Individual crosspoints, including the transmission transistor and the drive circuitry, are isolated by means of frame shaped p-type isolation regions lying outside the buried tub. The collector of the NPN drive transistor and the base of the PNP transmission transistor are ohmically connected by means of the buried tub. Accordingly, although the transmission transistor and the drive transistor are merged in a single isolation region, current drive to the PNP transistor is by means of the NPN transistor as a functionally independent device. The lateral PNP transistor comprises stripe shaped emitter and collector electrodes which are formed in a single step with the isolation region and the electrodes are of equal doping, size, and shape. Pluralities of such emitters and collectors which are respectively interconnected by surface metallizations may be utilized to increase the efficiency and the current carrying capacity of the transmission transistor.

Integrated semiconductor crosspoint arrangement

A semiconductor transmission circuit arrangement which utilizes symmetrical transmission transistors and bias circuitry which exhibits a high output impedance and is arranged to maintain equal d.c. bias currents in the base and the emitter/collectors of the transmission transistor. A multiple collector transistor is utilized as a primary current source and a current mirror circuit is used as a control arrangement.

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Glen Ellyn, IL, United States of America

James A Davis