Agere Systems Inc.

Ceridian Corporation

Avago Technologies International Sales Pte. Limited

James A Dahlberg

Jason P Brenden

Kermit E Frye

Ross Wilson

Jaydip Bhaumik

Obed Duardo

Derald A Pedersen

Larry M Werlinger

David G Fangmeier

Ross W Wilson

Various systems and methods for controlling DC motors are disclosed herein. For example, one method provides for controlling a polyphase, brushless DC motor. The method includes providing a DC motor that has a plurality of phases. Such a DC motor operates by inducing a current in the plurality of phases in accordance with a plurality of commutation states. In the example, six commutation states are discussed, but fewer than or more than six commutation states may exist. The method further includes initializing a count, inducing a current in the plurality of phases in accordance with a first commutation state, and incrementing the count until the current achieves a threshold in the first commutation state. Then, a current is induced in the plurality of phases in accordance with a second commutation state, and the count is decremented until the current achieves the threshold in the second commutation state. The sign bit of the count is stored, and a desired initial commutation state is determined based at least in part on the sign bit of the count.

Systems and methods for controlling a DC motor

A control apparatus controls retraction of a device carried on a moveable member actuated by an electric motor after a sudden power loss. The control apparatus includes a measuring circuit for measuring a back electromotive force (back EMF) from the electric motor during a measuring phase. The control apparatus also includes a controller which receives the actual velocity and provides a command signal for controlling a magnitude of the drive current based on a commanded velocity and the actual velocity of the moveable member. The control apparatus further comprises a current control loop for providing a command current signal based on the current provided to the electric motor and the command signal, and for providing the electric motor with the drive current during a driving phase based on the command current signal.

Velocity controlled disk drive head retraction after power loss

A control apparatus controls retraction of a device carried on a moveable member actuated by an electric motor. The control apparatus includes a measuring circuit with an output during a measuring phase including a back electromotive force (back EMF) from the electric motor plus a measuring circuit offset voltage. The control apparatus also includes an offset removing circuit connected to the output of the measuring circuit. The back EMF from the electric motor is provided at the output of the offset removing circuit. A driver circuit is connected to terminals of the electric motor for providing the electric motor with a drive current during a driving phase with a magnitude based on the back EMF from the electric motor.

Velocity controlled disk drive head retraction with offset removal

A disk drive emergency retract architecture for providing power to a voice coil motor (VCM) to retract a transducing head from a surface of a recordable medium during loss of power from an external power supply. The disk drive emergency retract architecture comprises a spindle motor, having an internal inductance and an internal resistance, for spinning the recordable medium. The spinning recordable medium creates a back electromotive force (BEMF) in the spindle motor. A boost circuit transfers the back electromotive force located in the spindle motor to a capacitor which stores and supplies power to the VCM. The capacitor is connected to a power switch circuit, which supplies power from the capacitor to the VCM when the power switch circuit is in a conducting state and prevents power from being supplied to by the capacitor to the VCM when the power switch circuit is in a non-conducting state. A retract circuit supplies a signal to the power switch circuit, dictating whether the power switch circuit is in the conducting state or the non-conducting state. The retract circuit operates to alternate the power switch circuit between the conducting state and the non-conducting state at a set frequency, resulting in power being provided from the capacitor to the VCM at this frequency.

Low cost emergency disk drive head retract architecture

A control circuit controls current through a voice coil motor (VCM) during retraction of a transducing head from the surface of a recordable medium. The transducing head is carried on movable member actuated by the VCM. The control circuit includes a measuring circuit for measuring a back electromotive force (back EMF) from the VCM. The control circuit also includes a driver circuit connected to terminals of the VCM for providing the VCM with a drive current having a magnitude based on the back EMF from the VCM. The control circuit further includes a chop clock to alternate between measuring the back EMF from the VCM and providing the VCM with the drive current at a random frequency within a range of frequencies around a median frequency.

Velocity controlled disk drive head retraction with reduced audible noise

A motor controller provides pulse width modulated drive signals to a motor. A digital demand code for controlling motor speed is input to the motor controller. A dither generator generates a digital dither value, which an adder adds to the demand code to generate a dithered demand code. A position determining circuit determines a rotational position of the motor. A pulse width modulation controller generates pulse width modulated drive signals with duty cycles controlled as a function of a stored set of waveform coefficients, the dithered demand code, and the rotational position of the motor.

Increased digital spindle motor control resolution through dither

A double data rate (DDR) synchronous dynamic RAM (SDRAM), or DDR-SDRAM, memory controller employing a delay locked loop (DLL) circuit to delay an SDRAM data strobe (DQS) signal to the center, or 'eye' of the read data window. However, in distinction from conventional techniques, the initial delay determined by the DLL is fine tuned with an offset determined by a memory test. Moreover, in an additional embodiment, the delay may be further adjusted during operation to compensate for environmental conditions by a PVT (process, value, temperature) circuit.

Programmable data strobe offset with DLL for double data rate (DDR) RAM memory

A direct memory access (DMA) controller having a first mode and a second mode controls communication between a module bus, communicating with a processor and a memory, and an input/output (I/O) bus communicating with an external device. A data controller subsystem stores I/O bus input data to provide module bus output data, and stores module bus input data to provide I/O bus output data. A device address controller subsystem stores a device address from the module bus to provide an I/O device output address to the I/O bus for addressing the external device. A memory addressing subsystem receives module bus input data to form an initial memory address provided to the module bus representing a storage location in the memory. An incrementer increments the initial memory address. In the second mode, the incrementer restarts the memory address at the initial memory address after incrementing the memory address a selected number of addresses above the initial memory address to form a wrap-around buffer in the memory. A transfer counter calculates a transfer count representing the number of selected data groupings of the I/O bus output data written into the memory. A detector detects when the transfer count reaches a selected value indicating that a normal DMA operation is complete in the first mode and detects when the wrap-around buffer in the memory is full based on the transfer count in the second mode.

DNA controller with wrap-around buffer mode

A priority selector prioritizes interrupts associated with each ASIC of a plural ASIC system in accordance with a programmed sequence. A table in each ASIC contains a programmable offset table and a programmable priority code table. The table selects an offset value and a priority code associated with the highest priority interrupt for the ASIC. An interrupt collector includes a priority compare to identify the priority code of the highest-priority interrupt of all of the ASICs. A multiplexer selects the offset value associated with it. The offset value forms a jump or offset address to the interrupt for the CPU. The priority sequencing, offset tables, priority code tables and priority compare values are programmable, so the prioritizing is adjustable. Each priority selector generates an interrupt active signal for the CPU. A mask disables interrupts until serviced by the CPU so that any interrupt active signal resulting from a disabled interrupt is terminated.

Programmable system for prioritizing and collecting central processor

A top state controller controls a bus adapter to a selected master or slave top state in response to a command on a local or system bus during a dispatch state of the bus adapter. The bus adapter remains in the selected top state until the command is completed or suspended, whereupon it returns to the dispatch state. The top state controller sets a first flag upon a change from a master top state to the dispatch state in response to suspension of a command by a data handling device, and sets a second flag upon a change from a slave top state to the dispatch state upon completion of a command. The top state controller is responsive to the first or second flag to operate the bus adapter to that master top state from which the bus adapter changed to set the first flag and is responsive to the completion of the suspended command to clear the first and said second flags. The controlled bus adapter and top state controller permit resolution of deadlock conditions and establish priorities between the local and system buses, and permit suspension of the master states to respond to slave commands.

Growing community of inventors

Eagan, MN, United States of America

James A Dahlberg