International Business Machines Corporation

Globalfoundries Inc.

Mentor Graphics Corporation

Other

Globalfoundries U.S. Inc.

James A Culp

Lars W Liebmann

Dureseti Chidambarrao

Maharaj Mukherjee

Praveen Elakkumanan

Kirk David Peterson

Mark Alan Lavin

Jason D Hibbeler

Scott Marshall Mansfield

Anthony D Polson

Jeffrey P Gambino

John J Ellis-Monaghan

Jed Hickory Rankin

Andrew Herbert Simon

Ronald G Filippi

Griselda Bonilla

Thomas W Dyer

Junjing Bao

Naftali Eliahu Lustig

Stephen Edward Greco

Paul S Chang

Samuel S Choi

Shayak Banerjee

Anda C Mocuta

Matthew S Angyal

Gregory Allen Northrop

John Maxwell Cohn

Werner A Rausch

Ulrich Alfons Finkler

Fook-Luen Heng

Rama Nand Singh

Leon Stok

Nakgeuon Seong

Laura S Chadwick

Jin Fuw Lee

Steven H Voldman

Kerry Bernstein

David James Hathaway

Alan Edward Rosenbluth

Timothy A Brunner

Jawahar P Nayak

Melanie J Sherony

Robert T Sayah

Ian P Stobert

Saibal Mukhopadhyay

Noah D Zamdmer

Pavan Y Bashaboina

Pieter J Woeltgens

Louis L Hsu

Rajiv V Joshi

Ying Liu

Shreesh Narasimha

Dirk Pfeiffer

Peilin Song

Kafai Lai

Robert L Wisnieff

Franco Stellari

Norman Jay Rohrer

Dongbing Shao

K Paul Muller

Paul Christian Parries

Fariborz Assaderaghi

Ioana C Graur

Dan Moy

Jerry D Hayes

James Allan Bruce

Rajeev Malik

Leah M P Pastel

Stephen Larry Runyon

Timothy G Dunham

Tina Jane Wagner

Patrick M Williams

Jacek G Smolinski

Alfred K Wong

Stephen E Fischer

David F Heidel

Christa Regina Willets

Azalia A Krasnoperova

Karen D Badger

Shaoning Yao

Ahmed Hassan

Chieh-yu Lin

Yuping Cui

Ming Yin

Atsushi Azuma

Marco Facchini

Pieter J Woltgens

John D Nickel

One illustrative system includes a processor and memory storing instructions that, when executed by the processor, cause the system to receive a device layout including a curvilinear feature, define a plurality of vertices for the curvilinear feature, determine a radius of curvature between a selected vertex in the plurality of vertices and a neighboring vertex in the plurality of vertices, and identify a design rule violation for the curvilinear feature responsive to the radius of curvature being less than a predetermined threshold.

Design-rule checking for curvilinear device features

Disclosed are methods, systems and computer program products that, during new technology node development, perform design rule and process assumption co-optimization using feature-specific layout-based statistical analyses. Specifically, the layout of a given feature can be analyzed to determine whether it complies with all of the currently established design rules in the new technology node. When the layout fails to comply with a current design rule, statistical analyses (e.g., Monte-Carlo simulations) of images, which are generated based on the layout and which illustrate different tolerances for and between the various shapes in the layout given current process assumption(s), can be performed. Based on the results of the analyses, the current process assumption(s) and/or the design rule itself can be adjusted using a co-optimization process in order to ensure the manufacturability of the feature within the technology.

Rule and process assumption co-optimization using feature-specific  layout-based statistical analyses

Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.

Semiconductor layout generation

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Selective local metal cap layer formation for improved electromigration behavior

Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed. To predict stress-induced displacements, the method inputs said density characteristics data into a programmed model that predicts displacements as a function of density, and outputs the predicted shift data.

Correcting for stress induced pattern shifts in semiconductor manufacturing

Various embodiments include computer-implemented methods, computer program products and systems for verifying an integrated circuit (IC) layout. In some cases, approaches include a computer-implemented method of verifying an IC layout, the method including: obtaining data about a process variation band for at least one physical feature in the IC layout; determining voltage-based process variation band thresholds for the at least one physical feature in the IC layout; determining whether the process variation band for the at least one physical feature in the IC layout meets design specifications for the IC layout based upon the voltage-based process variation band thresholds for the at least one physical feature in the IC layout; and modifying the IC layout in response to a determination that the process variation band for the at least one physical feature does not meet the design specifications.

Net-voltage-aware optical proximity correction (OPC)

An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.

Detecting chip alterations with light emission

Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Methods and system for analysis and management of parametric yield

A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.

Nitride etch for improved spacer uniformity

A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Physical design system and method

Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.

Yield enhancement by multiplicate-layer-handling optical correction

Growing community of inventors

Newburgh, NY, United States of America

James A Culp