Intel Corporation

James A Coleman

Ned M Smith

Francesc Guim Bernat

Gilbert A Neiger

Vedvyas Shanbhogue

Alexander Bachmutsky

Michael T Klinglesmith

Anil K Kumar

Rajkumar Khandelwal

Scott M Oehrlein

Alexander B Slota

Durgesh Srivastava

Hisham Shafi

Ramadass Nagarajan

Sunil K Cheruvu

Gary J Lavelle

Gerald Alan Rogers

Peter J Elardo

Joshua Ruggiero

Garrett Matthias Drown

Eric A Geisler

Philip C Arellano

Methods and apparatus for jitter-less distributed Function as a Service (FaaS) using flavor clustering. A set of FaaS functions clustered by flavor chaining is implemented to deploy one or more FaaS flavor clusters on one or more edge nodes, wherein each flavor is defined by a set of resource requirements mapped into a jitter Quality of Service (QoS) and is executed on at least one hardware computing component on the one or more edge nodes. One or more jitter controllers are implemented to control and monitor execution of FaaS functions in the one or more FaaS flavor clusters such that the functions are executed to meet jitter-less QoS requirements. Jitter controllers include platform jitter-less function controllers in edge nodes and a data center FaaS jitter-less controller. A jitter-less Software Defined Wide Area Network (SD-WAN) network controller is also provided to provide network resources used by FaaS flavor clusters and satisfy connectivity requirements between the edge nodes.

Jitter-less distributed function-as-a-service using flavor clustering

Technologies for managing low-latency network packet transmissions include an internet-of-things (IoT) device, or other networked device, depending on the embodiment, configured to determine a transmit mode of a network packet to be transmitted from the IoT device, wherein the transmit mode comprises one of a legacy network packet transmission mode or an immediate transmission mode. The IoT device includes a processor configured to write data of the network packet directly to a transmit buffer register of a network interface controller (NIC) of the IoT device subsequent to a determination that the transmit mode corresponds to the immediate transmission mode. Other embodiments are described herein.

Technologies for low-latency network packet transmission

Systems, methods, and apparatuses relating to processor non-write-back capabilities are described. In one embodiment, a processor includes a plurality of logical processors, a control register comprising a non-write-back lock disable bit, a cache shared by the plurality of logical processors, a bus to couple the cache to a memory to service a memory request for the memory from the plurality of logical processors, and a memory controller to disable a non-write-back lock access of the bus for a read-modify-write type of the memory request issued by a logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to a first value, and implement the non-write-back lock access of the bus for the read-modify-write type of the memory request when the non-write-back lock disable bit is set to a second value.

Apparatuses, methods, and systems for processor non-write-back capabilities

System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.

Fixed ethernet frame descriptor

A method may comprise identifying a signal indicating real-time mode operation for a guest operating system (OS) and directly routing an interrupt for a first processor to the guest OS while the guest OS is running without causing a transition from execution by the guest OS to execution by a host system. Other embodiments are disclosed and claimed.

Architecture and method for managing interrupts in a virtualized environment

This disclosure pertains to using traffic classes to selectively store data into cache memory or into system memory. A cache controller can map the traffic class of incoming data to portions of the cache memory allocated for corresponding traffic classes of data.

Method, apparatus, and system for allocating cache using traffic class

An apparatus and method are described for performing split lock operations in a multi-core processor. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions, each core comprising a core cache to cache data during instruction execution; a shared cache to be shared by two or more of the plurality of cores; a locking agent on a first core to initiate a split lock operation in response to detecting a transaction targeting at least two cache lines, the locking agent to transmit a request for the two cache lines to be set to an Exclusive state; at least one coherence enforcement engine to receive the request from the locking agent and to responsively cause any copies of the two cache lines in other cores to be invalidated; the locking agent to permit the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state and, upon completion of the transaction, to transmit an indication that the transaction is complete to the coherence enforcement engine.

Apparatus and method for non-serializing split locks

Use of hybrid error correcting code (ECC) techniques. A memory access request having an associated address is received. A memory controller determines whether the address corresponds to a first region of a memory for which ECC techniques are applied or a second region of the memory for which ECC techniques are not applied. The memory access is processed utilizing ECC techniques if the address corresponds to the first region of the memory, a transaction indicator and an execution unit indicator, and processed without utilizing the ECC techniques if the address corresponds to the second region of the memory.

Memories utilizing hybrid error correcting code techniques

Embodiments of apparatuses and methods for delivering real time interrupts with an APIC are disclosed. In one embodiment, an apparatus includes a local advanced programmable interrupt controller including a storage location to store a non-maskable interrupt vector.

Delivering real time interrupts with an advanced programmable interrupt controller

Apparatuses, methods and storage media associated with integrated circuits (IC) or system-on-chips (SOC) are disclosed herein. In embodiments, a multi-core IC may include a number of central processing units (CPUs), and a number of input/output (I/O) resources. The IC may further include a switch fabric configured to couple the CPUs with the I/O resources, and a register to be selectively configured to exclusively couple one of the CPUs with one of the I/O resources to form a logical domain that computationally isolates the one CPU and the one I/O resource from other CPUs and other I/O. Other embodiments may be described and claimed.

Growing community of inventors

Mesa, AZ, United States of America

James A Coleman