Sun Microsystems, Inc.

Cabletron Systems, Inc.

Alcatel Lucent

James A Bauman

Eric T Anderson

Philip Arnold Ferolito

Paul Chang

J Arjun Prabhu

Chakra R Srivatsa

Govind Kizhepat

A method and apparatus for supplying new requests to a scheduler in an input-buffered multiport switch involve selecting a request that does not target output channels that conflict with output channels targeted by requests that are already accessible to the scheduler. Specifically, target output channels of requests that are presently accessible to the scheduler are identified and compared to target output channels of requests that are included in a queue of next-in-line requests. The queue of next-in-line requests is reviewed and the highest priority request having no conflicting output channels is supplied to the scheduler. By supplying the scheduler with a new request that targets non-conflicting output channels, the scheduler is presented with a wider range of requested output channels from which to choose in each arbitration cycle. In a first embodiment, one, two, or eight ports are connected to each one of four input/output controllers in a switch having a four-channel switch fabric. To supply the scheduler with new requests, secondary arbitration is performed on a channel-specific basis in order to supply channel-specific requests to the scheduler. The method of supplying requests to the scheduler can be scaled to include multiple channels and multiple packet priority designations.

Method and apparatus for supplying requests to a scheduler in an input

A method and apparatus for controlling the flow of variable-length packets to a multiport switch involve accessing forwarding information in a memory based at least partially on layer 4 information from a packet and then forwarding the packet only if the packet is within a bandwidth consumption limit that is specified in the forwarding information. In a preferred embodiment, a credit bucket algorithm is used to ensure that packet flows are within specified bandwidth consumption limits. The preferred method for implementing the credit bucket algorithm to control flows of packets involves first receiving a particular packet from a flow and then stripping the layer 2 header information from the packet. The layer 3 and layer 4 information from the packet is then used to look-up flow-specific forwarding and flow control information in a memory that stores a linked list of table entries that includes the fields necessary to implement the credit bucket algorithm. The credit bucket algorithm is implemented in embedded devices within an application-specific integrated circuit, allowing the control of packet flows based on the application of the flow.

Method and apparatus for controlling the flow of variable-length packets

An IC includes a plurality of functional blocks each having a discrete block-level architecture. The functional blocks are connected to one another via metal interconnect lines defined by an interconnect architecture. One or more of the functional blocks includes a spare (i.e., unused) repeater amplifier. Where a repeater amplifier inserted in a particular long line of the interconnect structure would decrease the signal propagation delay through the long line, the interconnect architecture is modified so that the long line is routed through the spare repeater amplifier. Such modification decreases the signal propagation delay of the long line without requiring a modification of the block-level architecture.

Spare repeater amplifiers for long lines on complex integrated circuits

An apparatus and method of efficiently and dynamically generating the addresses associated with a set of instructions in a microprocessor pipeline is disclosed. Program counter age bits associated with the offsets of an address of a predetermined instruction within a set of instructions are used to indicate the chronological age of each instruction within the set of instructions. The age bits are generated by a logic circuit which also dispatches instructions to various execution units. The age bits are used to maintain and track the addresses of an instruction stream within a processing system so that there is no need to store the addresses of each and every instruction.

Program counter age bits

Certain bits in existing op code formats for a processor do not change from one instruction to another when particular classes of instructions are used. Applicants optionally utilize one or more of these bits to identify one of a plurality of different register files from which to retrieve operands or to store the results of an operation. These bits along with allocated address bits in predetermined address fields now allow the processor to address many more registers. This can be used to increase the performance of the processor. Those programs not utilizing the bits outside of the address fields for designating a particular register file are backwards compatible with the modified processor.

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San Jose, CA, United States of America

James A Bauman