International Business Machines Corporation

Jame Spiros Nakos

Chung H Lam

Glen L Miles

Christa Regina Willets

A logic chip including a non-volatile random access memory (NVRAM) array and method of fabrication thereof. The chip includes devices with gates on one or more of three polysilicon layers. Chip logic uses normal FETs and array support includes high voltage FETs. Both logic and support are CMOS. The gates of normal FETs in the chip logic are from the third, uppermost polysilicon layer. The third poly silicon layer also is used as a mask for high voltage FETs and array word lines, both of which use the second polysilicon layer for gates. The first polysilicon layer is used solely for cell floating gates.

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Essex Junction, VT, United States of America

Jame Spiros Nakos