Lucent Technologies Inc.

Agere Systems Guardian Corp.

Agere Systems Inc.

Broadcom Corporation

At+t Corp.

At&t Bell Laboratories

Jalil Fadavi-Ardekani

Walter G Soto

Kenneth Daniel Fitch

Bahram Ghaffarzadeh Kermani

Laurence Edward Bays

Richard J Niescier

Vafa James Rakshani

Lawrence John Madar, Iii

Avinash Velingker

David Lawson Potts

Vinay Bhasin

Chenmin Zhang

Srinivasa Gutta

Zhiqing Zhuang

Daniel K Greenwood

Joseph M Cannon

Donald Raymond Laturell

James Albert Johanson, Iii

Vladimir Sindalovsky

Eduardo Abreu

Frederick Harrison Fischer

Ravi Kumar Kolagotla

Jin-Der Wang

Weizhuang Wayne Xin

Hosahalli R Srinivas

Richard Niescier

Raymond S Livingston

Wayne Xin

Daisuke Takise

Geoffrey Lawrence Smith

Sonali Bagchi

Fan You

Soheyla Kamal, Legal Representative

A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external 'wake up event', will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

Method for managing and controlling the low power modes for an integrated circuit device

A multiple agent system providing each of a plurality of agents, e.g., processors, to access a shared synchronous or asynchronous memory. In the case of synchronous memory, the clock signal from a super agent selected from among the plurality of agents provides a memory access clock signal to the other agents accessing the same shared memory. The other agents synchronize their respective address, data and control busses to those of the super agent, and output a representation of the same clock signal to the shared memory. In another aspect of the present invention, the shared memory is partitioned for use from among a plurality of groups of agents, each agent group comprising one or more agents. Any one of the agents may update a configuration register to flexibly reconfigure the amount of shared memory available to the agents as necessary.

Dynamic partitioning of memory banks among multiple agents

The present invention provides a hardware accelerator of a DSP with a parameter RAM memory for storing the parameters required for the various operating conditions of the accelerator. The hardware accelerator can easily and without modification accommodate design changes such as the need to support additional ADSL lines.

Parameter memory for hardware accelerator

A transceiver for an asymmetric communication system is provided that implements a buffering and scheduling scheme that utilizes a virtual clock signal to synchronize processing of asynchronous frame data for multiple ADSL sessions. In every virtual clock cycle, the transceiver first sequentially performs transmit-processes for each active ADSL line and then sequentially performs receive-processes for each active ADSL line. An Asynchronous Transfer Mode (ATM) Acceleratol provides the network interface to multiple ATM channels and communicates frame data to a Frame Buffer (FB). The FB may be used in a ping-pang fashion for the communication of data between the ATM accelerator and a Framer/Coder/Interleaver (FCI), which performs its namesake, among other, functions. The FCI also interfaces a Digital Signal Processing (DSP) core through an Interleave/De-Interleave Memory (IDIM). The DSP core generates the virtual clock signal, which schedules operation of the ATM accelerator and the FCI. IDIM holds DMT frames of data and may also be utilized in a ping-pang fashion. Memory is shared by multiple ADSL sessions and by the transmit and receive processes within an individual session.

Multi-session asymmetric digital subscriber line buffering and scheduling apparatus and method

A multiple agent system providing each of a plurality of agents, i.e., processors, access to a shared synchronous memory. A super agent is preferably that agent from among a plurality of agents which accesses a shared synchronous memory most frequently. The super agent has direct access to the shared synchronous memory, without negotiation and/or arbitration, while the non-super agents access the shared synchronous memory under the control of an arbiter-and-switch. Open windows are generated when the super agent is not, accessing the shared synchronous memory. The non-super agents can be allowed interim access to the shared synchronous memory even, before the super agent terminates ownership of the shared synchronous memory.

Synchronous memory sharing based on cycle stealing

A memory paging method and apparatus using a memory paging register and a memory paging mask register. The invention has particular application in the partition of memory used by more than one software application program. The bits of the memory paging mask register selectably disable bits of the memory paging register to redefine the length and physical characteristics of pages in memory based on the needs of a software program. As a result, the paged partitions in memory may be of variable length and/or may comprise non-contiguous portions of the memory.

System for flexible memory paging in partitioning memory

A multiple agent system providing each of a plurality of agents, i.e., processors, access to a shared synchronous memory. A super agent is preferably that agent from among a plurality of agents which accesses a shared synchronous memory most frequently. The super agent has direct access to the shared synchronous memory, without negotiation and/or arbitration, while the non-super agents access the shared synchronous memory under the control of an arbiter and switch. Open windows are generated when the super agent is not accessing the shared synchronous memory. The non-super agents can be allowed interim access to the shared synchronous memory even before the super agent terminates ownership of the shared synchronous memory. In another aspect of the present invention, subsequent memory access request signals from an agent to the shared synchronous memory are suppressed for a minimum refractory period until a previously received acknowledge signal is cleared to prevent erroneous detection of memory access granted.

Multiple agent use of a multi-ported shared memory

The joystick port interface includes an integrated circuit receiving an analog joystick position measurement signal and outputting a digital pulse signal to a processor which signifies a joystick coordinate value. The integrated circuit includes a pulse generator and a bidirectional buffer circuit. The bidirectional buffer circuit receives the analog joystick position measurement signal and selectively discharges an RC network capacitor which provides this analog measurement. This implementation provides a joystick port which uses low-voltage CMOS VLSI structures which can interface a conventional high-voltage joystick with the processor.

Low-voltage joystick port interface

The present invention provides a game port interface having a second processor interface in addition to an otherwise conventional first processor interface such that a second processor may directly poll the game port interface to detect movement of a joystick device while a first, host processor is in a low power mode. Thus, the second processor may identify movement in the joystick and initiate a wake up sequence in the first, host processor via a communication path between the two processor interfaces. The additional processor interface allows the second processor to poll the joystick without interfering with the normal operation of the joystick. The present invention provides the power savings benefits of maintaining a host processor in a low power mode while at the same allowing another processor which may or may not be in a reduced power mode to detect movement of the joystick and initiate a wake up sequence in the host processor in response thereto.

System wake-up based on joystick movement

An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit. As long as the current value of the counter is less than or equal to the pre-programmed burst length, the burst control signal allows a clock controller to pass a master clock signal or other relevant clock signal as an instruction clock signal to the relevant processing unit. The low power burst mode and thus the power savings is adjustable according to the combined values of burst length and maximum counter value.

Processor powerdown operation using intermittent bursts of instruction clock

An improvement to split-architecture audio codecs such as those defined by the Audio Codec '97 specification (AC '97) includes an interrupt mechanism which allows an event at an analog peripheral device such as an incoming call to be sensed by the AC analog sub-system and initiate a wake up procedure in the split-architecture audio codec system. The interrupt mechanism includes a masked interrupt register which is responsive to an interrupt signal from an audio source, such as a ring detect from an incoming telephone line. Either the AC controller sub-system or the peripheral analog device via the AC analog sub-system can initiate a wake up procedure. The AC controller sub-system includes a static divide by 256 counter responsive to a bit clock signal. The bit clock signal is sensed at the AC controller sub-system to determine an operating mode. Upon detection of at least 256 bit clock cycles after a predetermined minimum time for the AC analog sub-system to be in a halted or sleep mode, a wake up interrupt register is enabled in the AC controller sub-system. The interrupt sensor is opto-coupled to the AC analog sub-system, and the interrupt signal from the interrupt sensor is communicated to the AC controller sub-system via the five-wire TDM serial bus between the AC analog sub-system and the AC controller sub-system.

Interrupt mechanism using TDM serial interface

A telephone adaptively updates its speed dial memory. For example, the telephone updates the speed dial memory based on a calling history. An example of a calling history based update according to the invention is to add frequently called telephone numbers to the speed dial memory and to drop infrequently called telephone numbers from the speed dial memory. Another example is to order the telephone numbers in the speed dial memory based on the frequency with which they are called.

Telephone with adaptive speed dial mechanism

An on-demand transfer (ODT) engine is located in each peripheral in a host/peripheral system communicating using a burst mode bus, e.g., a PCI bus. Each peripheral transfers blocks by setting, e.g., a starting address and block size of a data block to be transferred. Importantly, the starting location of a data transfer stream is maintained in a common memory area, e.g., in the host, while the length of the data transfer block is maintained in the ODT engine. By maintaining the length of the data block in the ODT engine, the peripheral can change the length of a block in a continual data stream on the fly, without the need to communicate with the host computer or common data transfer device such as a DMA. In the disclosed embodiment, up to 128 data streams may be simultaneously transferred.

On-demand transfer engine

A multiple agent system allowing each of a plurality of agents, i.e., processors, to present a different address, data, control and/or clock signals to a common shared synchronous memory. The signals from each of the agents is arbitrated in response to a memory access request to determine a winning agent. The address, data, control and clock signals to the shared synchronous memory are controlled so as to prevent undesirable high frequency waveforms and/or glitches from being presented to the shared synchronous memory during an arbitration period including a transition period between the previous owner's clock signal and the winning agent's clock signal. For instance, in the case of the clock signal, a clock switching control circuit disables the clock signal to the shared synchronous memory during the arbitration period for a period of time of at least about one phase of an arbiter clock signal before the transition period and one phase of the arbiter clock signal after the transition period. In the case of the address, data and control signals, an enable disactivation signal disables the output of the address, data and control signals to the shared synchronous memory during a transition period including the arbitration period.

Growing community of inventors

Orefield, PA, United States of America

Jalil Fadavi-Ardekani