International Business Machines Corporation

Jsr Corporation

Jrs Corporation

Jakub W Nalaskowski

Mahadevaiyer Krishnan

Michael F Lofaro

Tomohisa Konno

Tatsuya Yamanaka

Jason E Cummings

Dinesh Kumar Penigalapati

Dinesh R Koli

Masahiro Noda

Leslie Charns

Lukasz J Hupka

Takashi Ando

Josephine B Chang

Michael A Guillorn

John Michael Cotte

Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.

Chemical mechanical planarization with overburden mask

A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

Chemical mechanical planarization processes for fabrication of FinFET devices

Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

Fabrication of replacement metal gate devices

A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.

Shallow trench isolation chemical mechanical planarization

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Jakub W Nalaskowski