International Business Machines Corporation

Massachusetts Institute of Technology

Jakub Tadeusz Kedzierski

Cyril Cabral, Jr

Diane Catherine Boyd

Thomas Safron Kanarsky

Bruce Bennett Doris

Meikei Ieong

Vijay Narayanan

An L Steegen

Victor Ku

Ricky S Amos

Ying Di Zhang

Ying Li

Anda C Mocuta

Richard D Kaplan

Woo-Hyeong Lee

Kevin K Chan

Min Yang

MeiKei Leong

Raymond M Sicina

Maheswaren Surendra

Christian Lavoie

Rahul Sarpeshkar

Todd A Thorsen

Maheswaran Surendra

Sunfei Fang

Mahender Kumar

Benjamin I Rapoport

Hasan Munir Nayfeh

Jeremy Bert Muldavin

Katayun Barmak

Michale Sean Fee

An actuator with a stack of thin layers operates by electrowetting droplets between the layers. The actuator includes a first layer structure and a second layer structure positioned adjacent to the first layer structure. One or more liquid droplets are pinned to one of the layers and are positioned between the layers. The other layer includes electrodes. When the electrodes are energized, they electrostatically attract the liquid droplets to create relative motion between the two layers.

Multilayered microhydraulic actuators

A glucose fuel cell for reception into a given constrained volume of implantation in a vertebrate in which the glucose fuel cell has access to fluid containing glucose. The fuel cell includes an anode adapted to oxidize the glucose, a cathode adapted to reduce an oxidant, and a membrane disposed between the anode and the cathode and separating the anode from the cathode. At least one of the anode or cathode define a flexible sheet that is geometrically deformed to be receivable into the given constrained volume of implantation and increase volumetric power density. Related methods of making a glucose fuel cell of this type and implantable assemblies including the glucose fuel cell are also disclosed.

Flexible and implantable glucose fuel cell

In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.

Ultra thin silicon on insulator

In one embodiment, the invention is a method for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.

Method for fabricating an ultra thin silicon on insulator

A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

Sectional field effect devices and method of fabrication

The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

CMOS silicide metal gate integration

Method of fabricating sectional field effect devices

Sectional field effect devices

The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

Hybrid planar and FinFET CMOS devices

A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.

Method and apparatus for fabricating CMOS field effect transistors

A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.

Metal gate MOSFET by full semiconductor metal alloy conversion

A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated with fabricating a CMOS structure containing silicide contacts and silicide gate metals.

Method for integration of silicide contacts and silicide gate metals

Hybrid planar and finFET CMOS devices

Growing community of inventors

Peekskill, NY, United States of America

Jakub Tadeusz Kedzierski