Integrated Device Technology, Inc.

Intel Corporation

Jakob Saxtorph

John Raymond Mick, Jr

Harmeet Bhugra

Brian Scott Darnell

Bertan Tezcan

Kenneth Branth

William Terry Beane

Jian Hu

Kailash Kamana

Shriram Deshpande

Angus David Starr Macadam

This disclosure describes systems, methods, and devices related to providing video coding mode decisions to multiple video codecs. A method may include receiving, at a first engine of a graphics processor, intra coding mode candidates associated with generating bitstreams of coded video; receiving, at the first engine, inter coding mode candidates associated with generating the bitstreams; receiving, at the first engine, palette coding mode candidates associated with generating the bitstreams; generating, by the first engine, based on rate distortion estimates associated with the received candidates, coding mode decisions associated with generating the bitstreams; sending, by the first engine, the coding mode decisions to a second engine of the graphics processor and to a third engine of the graphics processor, the second engine using a first codec and the third engine using a second codec different than the first codec; generating the encoded bitstreams based on the coding mode decisions.

Enhanced video coding using a single mode decision engine for multiple codecs

In accordance with the present invention is provided a system and method for improving a timestamp precision in a precision timestamp protocol (PTP) device. The present invention provides for dynamic adjustment of otherwise uncertainty of the latency of a connection between two devices connected together through a gearbox and/or a block sync circuit. The dynamic adjustment is accomplished by identifying the alignment of data within the gearbox and block sync and adjusting the timestamp assigned to the data based upon the identified alignment to remove the jitter associated with the gearbox and the block sync, thereby improving the timestamp precision in the PTP device. In a particular embodiment, the invention is employed in a serial-deserializer (SERDES) device.

System and method for improving the timestamp precision in a precision time protocol (PTP) device

CAM-based search engines may be configured to support multiple databases within a CAM core. These databases may represent tables for different applications, which can be searched sequentially in response to a single indirect instruction that is loaded during a control cycle. The databases to be searched may be identified by a multi-database search instruction that is loaded during a single data cycle, which may overlap with the control cycle. In some cases, the databases may be searched using variations of a primary search key, so that it is unnecessary to repeatedly load the entire search key across a network interface for each search operation within a respective database. Instead, shorter replacement key segments may be loaded for each of a plurality of the search operations and these replacement key segments may be combined with one or more segments of the primary search key in the CAM core to define a desired search key for a respective search operation.

CAM-based search engines that support pipelined multi-database search operations using encoded multi-database identifiers

CAM-based search engine devices operate to reduce the occurrence of duplicate learned entries within a CAM database when processing search and learn (SNL) instructions. A search engine device may be configured to support processing of first and second immediately consecutive and equivalent SNL instructions as a first SNL instruction and a second search and search instruction, respectively. This processing is performed in order to block an addition of a duplicate learned entry within a database in the search engine device. The search engine device may also be configured to selectively block processing of the second SNL instruction as a second search and search instruction in response to detecting the database as full when the first SNL instruction is processed.

CAM-based search engine devices having advanced search and learn instruction handling

An integrated circuit chip includes a search engine including a content addressable memory (CAM) configured to produce CAM indices responsive to search instructions provided to the search engine. The search engine further includes an index translation circuit operatively coupled to the CAM and configured to provide translation of the CAM indices to another memory space, such as from an absolute index space associated with the CAM to a memory space associated with a database within the CAM or to a memory space of a device external to the chip, such as a command source or external SRAM.

CAM-based search engine devices having index translation capability

Integrated search engine devices include a content addressable memory (CAM) core that is configured to support at least one database of searchable entries therein and a control circuit. The control circuit is configured to support reporting to a command host of data identifying entries that have been aged out of the at least one database and/or entries that have exceeded an activity-based aging threshold. The control circuit is further configured to support age reporting that is programmable on a per entry basis within the at least one database.

CAM-based search engines having per entry age reporting capability

CAM-based search engines that support pipelined multi-database search operations using replacement search key segments

An ATM switch according to the present invention includes a memory and a control circuit. The ATM switch generates a connection table in a memory, generates a multicast master entry including a limit field and a count field. The multicast master entry also includes address locations at which multicast ATM cells are stored. The ATM switch further generates one or more multicast member entries associated with said multicast master entry in said connection table, each multicast member entry identifying a destination connection on which said multicast ATM cells are to be transmitted. Further, the count field is initialized and the limit field is set at a predetermined value. The master entry is then determined to be active or inactive depending on a comparison between the count field and the limit field.

Detection and recovery from connection failure in an ATM switch

Content addressable memory (CAM) devices include CAM logic that is configured to pass an instruction received at an instruction input port to an instruction output port without inspection or alteration. This enables the CAM devices to be operated as equivalent devices within a cascaded chain of CAM devices that collectively form multiple databases within a lookup engine having distributed CAM control. This CAM logic may include an input instruction register that is configured to latch the instruction received at the instruction input port and an output instruction register that is configured to latch the instruction received from the input instruction register. This CAM logic may also include an instruction FIFO that is configured to buffer instructions received from the input instruction register. A method of performing a learn operation in a cascaded chain of CAM devices may include writing a search key associated with a database into a selected one of the cascaded chain of CAM devices, in response to evaluating whether an NFA table in the selected one of the cascaded chain of CAM devices has a valid NFA address for the search key. Then, following the write operation, an operation may be performed to search each of the CAM devices in the cascaded chain to identify an address of a highest priority invalid entry in a CAM device that retains at least a portion of the database.

Content addressable memory (CAM) devices that support distributed CAM control and methods of operating same

An ATM switch for transmitting a multicast ATM cell includes a memory, a control circuit, and a cell memory. The control circuit maintains in the memory a connection table which includes a multicast master entry and one or more multicast member entries associated with the multicast master entry. The cell memory stores one or more ATM cells, including the multicast ATM cell. The multicast master entry holds an address of the cell memory at which the multicast ATM cell is stored. The multicast member entries are linked to each other through a circular double linked list.

Growing community of inventors

San Jose, CA, United States of America

Jakob Saxtorph