Infineon Technologies Ag

Siemens Aktiengesellschaft

Jakob Huber

Ewald Pettenpaul

Klaus Diefenbeck

Klaus Gnannt

Carsten Ahrens

Wolfgang Klein

Ulrich Krumbein

Uwe Seidel

Christian Herzum

Karlheinz Mueller

Karlheinz Müller

Wolfgang Meier

Knut Brenndoerfer

Herbert Weidlich

Felix Petz

A method for manufacturing an electrical device is disclosed. In an embodiment, the method includes providing a first layer of a first conductivity type, providing an intrinsic layer onto the first layer, providing one or more trenches into the intrinsic layer, filling the one or more trenches with a material of a second conductivity type opposite to the first conductivity type, and providing a second layer of a second conductivity type onto the intrinsic layer.

Electrical device and method for manufacturing same

An electrical device includes a first layer, a second layer and an intrinsic layer. The first layer is of a first conductivity type, wherein the second layer is of a second conductivity type opposite to the first conductivity type. The intrinsic layer is arranged between the first and the second layer and has a reduced thickness at at least one portion. An area of the at least one portion is less than 50% of an active area in which the first and second layer face each other.

A transistor assembly having a transistor includes a plurality of transistor regions, each of which has a vertical transistor structure having a collector semiconductor region, a base semiconductor region and an emitter semiconductor region, emitter contacting regions arranged above the transistor regions and base contacting regions connected to the base semiconductor regions via a polycrystalline semiconductor layer, wherein the polycrystalline semiconductor layer is structured such that the base contacting regions of transistor regions which are not part of the transistor are electrically isolated from base contacting regions of transistor regions which are part of the transistor.

Transistor assembly and method for manufacturing same

A method for producing a contact structure on a structured surface comprising producing a first conductive layer on the structured surface, wherein the first conductive layer comprising tungsten. A conductive seed layer is produced on the first conductive layer, the contact structure being produced by electroplating on the seed layer. The first conductive layer serves as an etch stop for selectively removing substrate material from the backside.

Method for fabrication of a contact structure

A semiconductor structure including a substrate, a device layer and a contact arranged on the substrate, comprises an ESD protective means, arranged between the substrate and the contact, such, that in the ESD case a breakthrough from the ESD protective means to the contact occurs.

Semiconductor structure comprising an electrostatic discharge (ESD) protection device

A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Semiconductor structure and method for improving its ability to withstand electrostatic discharge (ESD) and overloads

A semiconductor component and a method for fabricating it includes a substrate and an epitaxial layer situated thereon and integrating at least a first and a second bipolar component in the layer. The first and second bipolar components have a buried layer and different collector widths. The buried layer of the second component has a larger layer thickness than that of the first component; exactly one epitaxial layer is provided. The different collector widths produced as a result thereof are influenced by the outdiffusion of the dopant of the buried layers by other substances.

Semiconductor component and method for fabricating it

A bipolar silicon transistor includes at least one emitter zone with n.sup.+ arsenic doping and with a phosphorus doping. The ratio between arsenic dopant concentration and phosphorus dopant concentration is between 10:1 and 500:1 in the at least one emitter zone. The at least one emitter zone may also have a penetration depth of less than 0.5 .mu.m. A method for producing a bipolar silicon transistor includes implanting a n.sup.+ -doped emitter zone with arsenic, implanting the n.sup.+ -doped emitter zone with phosphorus, setting a ratio in the n.sup.+ -doped emitter zone between the arsenic dopant concentration and phosphorus dopant concentration to between 10:1 and 500:1, and annealing crystal defects.

Bipolar Silicon transistor with arsenic and phosphorous ratio

A high-frequency transistor has a suitably doped and structured semiconductor chip (1) that is composed of a doped Si substrate and has base, collector and emitter contactings (2, 3, 4). The chip (1) is surrounded by a housing (8), the contacts being connected to the respective base, collector and emitter terminals (6, 7, 5) of the housing. With the housing the transistor has a high gain at frequencies above 1 GHz. The base, collector and emitter contacts (2, 3, 4) are provided at the upper side of the semiconductor chip (1). The semiconductor chip (1) has its underside arranged on the emitter terminal (5) of the housing (8) which is fashioned as HF ground. The emitter contact (4) is connected over a short distance to the emitter terminal (5) of the housing (8). The base and collector contacts (2, 3) are each respectively connected via at least one bond wire (9) to the respective base or collector terminals (6, 7).

Bipolar high-frequency transistor

A semiconductor diode has three adjacent regions. The doped regions are doped in the same manner and are separated from one another by a third, intrinsic region. The intrinsic region is dimensioned such that upon application of a specific external voltage at the operating temperature of the diode, it is possible for charge carriers to tunnel from one doped region to the other doped region through the intrinsic region. The semiconductor diode has a planar structure on a semiconductor substrate. A semconductor diode of this kind is suitable for use as a protective diode for other components, particularly when they are mounted on substrates consisting fo connecting semiconductors.

Semiconductor diode and method for making it

In a monolithically integratable microwave attenuation element, the attenuation is switchable between various, discrete values and the signal experiences only a small phase shift when switched between the individual attenuation values. The drain-source paths of field effect transistors (Q1, Q2, Q3) in the attenuation element are arranged in a PI configuration. Resistors (R11, R22, R33) are connected parallel to the drain-source paths of the field effect transistors (Q1, Q2, Q3) that are arranged in PI configuration.

Monolithically integratable microwave attenuation element

A chain amplifier assembly, includes a semiconductor body, a chain amplifier disposed in the semiconductor body and having an input, an output, a plurality of interconnected amplifier stages having transition regions therebetween, each of the stages including a plurality of field-effect transistors having source, gate and drain terminals, each of the source terminals being connected to a given common source potential, a plurality of ohmic resistors and inductances connected in series between the gate terminals forming a gate line, a plurality of capacitances each having a lead connected in parallel to the gate line and another lead connected to the given common source potential, a plurality of inductances connected in series between the drain terminals forming a drain line, a plurality of additional ohmic resistors having a lead connected in parallel to the drain line and another lead connected to the given common source potential, a plurality of additional capacitances having a lead connected in parallel to the drain line and another lead connected to the given common source potential, matching elements in the form of capacitances, inductances and ohmic resistors connected at the input, output and transition regions, the drain and gate lines being wave guides formed with metal coatings, insulating coatings and doping concentrations required for the field-effect transistors, and additional circuit elements monolithically integrated into the semiconductor body.

Chain amplifier

Fabricating a semiconductor arrangement with a semiconductor body of an A.sub.III -B.sub.V compound, characterized that the semiconductor body is doped with different doping substances in such manner that for barrier and non-barrier contacts on different zones doped with these doping substances only one metallization is required.

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Beyharting, Germany

Jakob Huber