Micron Technology Incorporated

Micron Display Technology, Inc.

Jake Baker

Glen Earl Hush

Tom W Voshell

Glen F Hush

John T Moore

John Moore

A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.

Complementary bit PCRAM sense amplifier and method of operation

A method and apparatus are disclosed for sensing the resistance state of a resistance-based memory element using complementary resistance-based elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.

Method of operating a complementary bit resistance memory sensor and method of operation

The present invention relates to a method and apparatus for sensing the resistance state of a programmable resistance memory, using complementary memory elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the resistance elements to determine the resistance state of an element being read.

Method of operating a complementary bit resistance memory sensor

Complementary bit resistance memory sensor and method of operation

A programmable conductor memory cell is read by a sense amplifier but without rewriting the contents of the memory cell. If the programmable contact memory cell has an access transistor, the access transistor is switched off to decouple the cell from the bit line after a predetermined amount of time. The predetermined amount of time is sufficiently long enough to permit the logical state of the cell to be transferred to the bit line and also sufficiently short to isolate the cell from the bit line before the sense amplifier operates. For programmable contact memory cells which do not utilize an access transistor, an isolation transistor may be placed in the bit line located between and serially connection the portion of the bit line from the sense amplifier to the isolation transistor and the portion of the bit line from the isolation transistor to the memory cell. The isolation transistor, normally conducting, is switched off after the predetermined time past the time the bit line begins to discharge through the programmable contact memory cell, thereby isolating the programmable contact memory cell from the sense amplifier before a sensing operation begins.

PCRAM rewrite prevention

A circuit and method for producing a walking one pattern in a shift register. The circuit comprises a shift register and a NOR gate. The NOR gate output is connected to the data input of the shift register, and the data output of each of said register stages is connected to a respective one of the NOR gate inputs.

Producing walking one pattern in shift register

A matrix display maintains synchronization with an input NTSC composite video signal by combining the functions of a phase locked loop, a column selector, and a row selector. The matrix includes display cells arranged in rows and columns, each display cell enabled for display on receipt of a column pointer signal and a row pointer signal. The column selector includes a shift circuit that shifts a walking-one pattern to assert in turn one column pointer signal at a time for each column in the matrix. An overflow signal from the shift circuit is used for three functions: (1) to reinstate the walking pattern in the column selector, (2) to lock the phase locked loop on the horizontal synchronization pulse of the NTSC signal, (3) to clock the row selector. The row selector includes a shift circuit and walking-one pattern to assert in turn one row pointer signal for each row of the matrix. Vertical synchronization is maintained by recording several samples of the NTSC signal taken after successive horizontal synchronization pulses, and selectively disabling the phase comparator of the phase locked loop. In a preferred embodiment, the matrix display includes field emission display cells arranged with all support circuitry on an integrated circuit substrate. Shift circuits, consisting of low power dynamic shift stages, eliminate conventional counter circuitry saving surface area on the substrate and reducing heat and power consumption.

Timing control for a matrixed scanned array

A serial to parallel conversion circuit uses a dynamic shift register in a phase locked loop for an index to access a parallel holding register. The composite input signal includes serial data to be sampled and a synchronizing signal at an integer factor of the sampling serial data rate. The phase locked loop generates a control signal for sampling the serial data at a multiple of the synchronizing frequency by incorporating a delay between a variable frequency oscillator output and a phase comparator input. The delay element in one embodiment includes a shift register with a walking-one pattern that overflows to the phase comparator. The walking-one pattern is used to identify which position of the holding register should store the next sample of the input signal. The shift register is self-initialized by a logic combination of all shift register outputs. Power dissipation by the serial to parallel conversion circuit is minimal because only one 7-transistor shift register cell draws current at a time.

Growing community of inventors

Meridian, ID, United States of America

Jake Baker