Nvidia Corporation

Jaison Daniel Kurien

Shantanu Sarangi

Milind Bhaiyyasaheb Sonawane

Sailendra Chadalavada

Venkat Abilash Reddy Nerallapally

Bonita Bhaskaran

Purnabha Majumder

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

Growing community of inventors

Bengaluru, India

Jaison Daniel Kurien