Honeywell Information Systems Inc.

Honeywell Bull, Inc.

Jaime Calle

Garvin Wesley Patterson

Earnest M Monahan

Jerome J Twibell

Lawrence W Chelberg

Victor Michael Griswold

William A Shelly

Marion G Porter

John M Woods

Knute S Crawford

Edwin W Herron

Lawrence J Kristick

V Michael Griswold

Robert J Garvey

Frederick D Strout

George L Parris

A data processing system includes a first and a second central system wherein the central processing unit (CPU) of the first central system is operatively connected to the system control unit (SCU) of the second central system and the CPU of the second central system is operatively connected to the SCU of the first central system, each central system including a service processor and a timing subsystem for providing clocking signals. Each central system includes an apparatus for distributing the clocking signals such that each central system is clocked from predetermined ones of the clocking signals in response to control signals from the service processors. The apparatus permits the distribution of the clocking signals to be switched dynamically while the central systems are operating, the switching of the clocking signals being accomplished without affecting the operation of the central systems. The apparatus comprises a generating element for generating local clocking signals. A first logic element generates a stop signal at a predetermined time relative to the local clocking signals in response to predetermined ones of the control signals. A gating element conditionally outputs the local clocking signals in response to the stop signal. A selector which receives remote clocking signals from the timing subsystem of the other central system selectively outputs the local clocking signals or the remote clocking signals in response to the predetermined control signals, the control signals being modified during a time period that the stop signal is active, thereby permitting the selector to select alternate clocking signals before the stop signal becomes inactive thereby switching the source of the clocking signals which are clocking the central systems without perturbing the tasks being executed in the central systems.

Apparatus for dynamically switching the clock source of a data

An input/output system includes a plurality of modules and a system interface unit having a plurality of ports, each of which connects to a different one of the modules. The plurality of modules includes at least one processor and one memory module. The system interface unit includes a timer unit and a priority network for processing processor interrupt requests on a priority basis. The priority network connects to a register for storing coded priority level signals to be assigned to the different types of interrupt requests. The register is conditioned to store a low priority level for timer interrupts. The timer unit includes a preset register, an interval counter and a rollover counter. At the completion of each time interval, the interval counter is loaded automatically from the preset register and counting is continued. Simultaneously, the interval counter conditions the rollover counter to store a count registering the total number of completed intervals counted. The processor responds to a timer interrupt request by a special command which can only selectively clear the rollover counter to ZEROS when the interval counter is not in the process of completing another interval.

Interval timer for use in an input/output system

An input/output system includes a local memory module including a cache store and a backing store. The system includes a plurality of command modules and a system interface unit having a plurality of ports, each connected to a different one of the command modules and to the local memory module. The cache store provides fast access to blocks of information previously fetched from the backing store in response to memory commands generated by any one of a plurality of command modules during both data transfer and data processing operations. The local memory module includes apparatus operative in response to each memory command to enable the command module to write into cache store the data which is requested to be written into backing store when it is established that such data has been previously stored in cache store.

Cache write capacity

An input/output system couples to a host processor through a system interface unit and includes at least two input/output processing units and a memory unit. The system interface unit includes interrupt processing logic circuits for each input/output processing unit for processing interrupt requests on a priority basis. The system interface unit further includes a processor intercommunication network which connects to each of the interrupt processing logic circuits. The input/output operating system initiates an input/output operation in response to a connect interrupt generated by the host processor executing a connect instruction. The interrupt is directed to an assigned input/output processing unit by the System Interface Unit (SIU). The assigned processor executes an instruction sequence which causes an appropriate entry to be placed in an operating system queue located within the memory unit. The queue entry has sufficient data to specify the desired I/O operation. The processing unit in control stores information in the memory unit to specify the interrupt priority level of the connect operation, sets an interrupt request at that same priority level, and causes an interrupt at a very high priority level for the other processing unit via the intercommunication network. The high priority level interrupt causes the other processing unit to execute instructions which load the priority level information from the memory unit and set an interrupt request at the specified level. With both processing units having outstanding interrupt request at the specified priority level, the processing unit which completes all of the processes at priority levels higher or equal to that of the queue entry responds to the interrupt first. By having the least busy processing unit respond to the interrupt utilizing the queue entry to initiate the desired input/output operation process, a balance in the utilization of the input/output processing units is insured.

Balancing the utilization of I/O system processors

A local memory of an input/output system includes a cache store and a backing store. The system includes a plurality of command modules. The cache store provides fast access to blocks of information previously fetched from the backing store in response to memory commands generated by any one of a plurality of command modules during both data transfer and data processing operations. Each memory command applied to the memory unit incudes a predetermined bit which is coded to designate when the information requested from the local memory unit is to be written into the cache store. The local memory unit includes aparatus operative in response to each memory command to enable the command module to bypass selectively the cache store in accordance with the coding of the predetermined bit thereby enabling the command modules to execute operations more expeditiously during the performance of input/output data transfer operations.

Input/output cache system including bypass capability

An automatic reconfiguration hardware capability for automatically altering the local memory/processor configuration and reinitiating a bootload sequence in the event of a failure in the start-up phase of the input/output processor bootload. The automatic reconfiguration logic is enabled when a bootload request originates from the system console or the central system. Once a bootload request is initiated, all possible local memory/input-output processor (IOPP) configurations are attempted without further manual intervention. If no configuration is successful, a bootload error indication is presented at the I0P configuration panel.

Automatic reconfiguration apparatus for input/output processor

Priority interrupt apparatus includes a level priority network, a plurality of priority networks, and selector circuits, each corresponding in number to the number of channel sources operative to generate interrupt requests. Each priority network receives requests signals corresponding to different types of possible event signals requiring attention and produces a type code designating the highest priority event from the channel associated therewith. The priority is established in accordance with a preassigned event priority approximating the priorities assignable by program. Each of the selector circuits is connected to receive as a control input the type code signals generated by the priority network associated therewith. Additionally, each selector circuit receives a different set of interrupt level number signals representative of priorities assigned by program to the number of possible event signals. In response to the request signals, the selector circuit of each channel source applies as an input to the level priority network the programmed designated set of interrupt level number signals specified by the type code signals. The level priority network includes a number of compare circuits and output gating circuits. Each compare circuit provides signal indications as to which one of a pair channels has the higher priority event as defined by the selected interrupt level signals. Signals indicating the results from each compare circuits are then applied to the output gating circuits which generate a code for selecting the type code and interrupt level signals of the channel source receiving the highest priority event.

Priority interrupt logic circuits

An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command signals and at least one multiplexer unit which directly controls transfers between the memory module and any one of a plurality of peripheral devices coupled to different ports of the multiplexer unit. The system interface unit operatively provides connections between different ones of the modules during the execution of commands included within user programs. The multiplexer unit includes sets of registers selectable under program control which store information which enables user programs for accessing the memory module. Additionally, other ones of these registers store control information used to control the processing of interrupts as well as other operations independently of user programs. The multiplexer unit includes apparatus which operatively couples these registers and is responsive to commands to ensure that only authorized acceses to these registers are made during system operation. The system also provides access rights to those registers to different types of system software such that only the system routines having the appropriate privileges are able to transfer information to those registers within the multiplexer unit.

Input/output multiplexer security system

A firmware/hardware mechanism in a general purpose computer system automatically provides alternate addressing paths for addressing data in the same or another main memory module when a failure is detected in a portion of the main memory or main memory module. Two types of memory failures are detected and an alternate path provided for each type of failure. The first type is a failure in a memory which is not detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an exception processing mechanism to provide an alternate path to a good memory module. The second type of failure is detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an interrupt processing mechanism to provide an alternate path to a good memory module.

Fail soft memory

An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations. Each multiplexer unit includes a plurality of storage registers which are operatively coupled to the programmable interface associated therewith for receiving control information therefrom designating the priority to be given by the unit to the processing of different types of interrupt signals received from devices associated therewith in addition to information designating which one of a set of processing routines to be used in servicing the interrupt.

Programmable interface apparatus and method

High density data storage is permitted on magnetic disk by providing uniform length data sectors and by grouping a plurality of data sectors with a single header. Any data sector may be accessed through location of the desired group header and counting to the position of the sector.

High density data storage on magnetic disk

Priority interrupt hardware monitors for the existence of, and determines the relative importance of requests to determine or attempt to determine when to interrupt an executing process on a processor. The processor may be interrupted only when the hardware determines that something more important needs to be done than what is being done by the currently executing process. Additionally, the processor may set interrupts for itself so that a portion of an executing process may be executed at a higher priority than that required for the remaining portion of the same process.

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Glendale, AZ, United States of America

Jaime Calle