Apple Inc.

Jaidev P Patwardhan

John Gregory Dorsey

Daniel Allen Chimene

Bryan R Hinch

Kushal Dalmia

Ronit Banerjee

Matthias Knoth

Constantin Pistol

Dmitriy B Solomonov

Matthew C Widmann

Shekhar S Srikantaiah

Prakhar Malhotra

Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.

Performance islands for CPU clusters

An apparatus includes a processor circuit that includes a memory circuit, one or more processor cores, and a debug circuit. The debug circuit may be configured, in response to activation of a trace mode to record information indicative of instructions executing on the one or more processor cores, to write a trace data stream to the memory circuit that includes trace data collected on the instructions executing on the one or more processor cores. In response to a particular instruction within one of the processor cores specifying a write of a data value to an architecturally visible trace register, the debug circuit may be further configured to output the data value to the trace data stream as part of executing the particular instruction.

Hardware support for software event collection

Embodiments include an asymmetric multiprocessing (AMP) system having a first central processing unit (CPU) cluster comprising a first core type, and a second CPU cluster comprising a second core type, where the AMP system can update a thread metric for a first thread running on the first CPU cluster based at least on: a past shared resource overloaded metric of the first CPU cluster, and on-core metrics of the first thread. The on-core metrics can indicate that first thread contributes to contention of the same shared resource corresponding to the past shared resource overloaded metric of the first CPU cluster. The AMP system can assign the first thread to a different CPU cluster while other threads of the same thread group remain assigned to the first CPU cluster. The thread metric can include a Matrix Extension (MX) thread flag or a Bus Interface Unit (BIU) thread flag.

CPU cluster shared resource management

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Mountain View, CA, United States of America

Jaidev P Patwardhan