Samsung Electronics Co., Ltd.

Jai-Dong Lee

Jung-Hwan Kim

Hun-Hyeoung Leam

Young-sub You

Woong Hee Lee

Ki-Su Na

Young-Seok Kim

Won-Jun Jang

Yong-Sun Lee

Chang-Hyun Ko

Sang-Hoon Lee

Sang-Hun Lee

Ki-chul Kim

In-Wook Cho

Bong-hyun Kim

Ki-hyun Hwang

Hyun-Jin Shin

Yong-Woo Hyung

Man-Sug Kang

Seung-Mok Shin

Won-Seok Yoo

Jin-Hee Lee

In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.

Methods of forming void-free layers in openings of semiconductor substrates

In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.

Method of forming a gate structure for a semiconductor device and method of forming a cell gate structure for a non-volatile memory device

Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

Methods of manufacturing a semiconductor device

A method of forming a floating gate of a non-volatile memory device can include etching a mask pattern formed between field isolation regions in a field isolation pattern on a substrate to recess a surface of the mask pattern below an upper surface of adjacent field isolation regions to form an opening having a width defined by a side wall of the adjacent field isolation regions above the surface. Then the adjacent field isolation regions is etched to increase the width of the opening.

Methods of forming self-aligned floating gates using multi-etching

A method for manufacturing a dielectric layer structure for a non-volatile memory cell is provided. A method includes forming a first dielectric layer for tunneling on a semiconductor substrate, a second dielectric layer on the first dielectric layer to store charges, nitrogenizing surface of the second dielectric layer, and forming a third dielectric layer the nitridedsecond dielectric layer.

Method of manufacturing a dielectric layer in a memory device that includes nitriding step

Methods of fabricating a floating gate of a flash memory cell are provided in which a first polysilicon layer is formed between first and second isolation layers. An upper region of the first polysilicon layer is then oxidized. The oxidized upper region of the first polysilicon layer is subsequently removed. A second polysilicon layer is formed on the first polysilicon layer. The second polysilicon layer and the first polysilicon layer are patterned to form the floating gate.

Methods of fabricating flash memory devices with floating gates that have reduced seams

A system and method for real time deposition process control based on resulting product detection, where the system and method detect an amount of at least one reaction product in real time, while the deposition process is being performed, the detected amount of reaction product is compared with a reference amount, and a comparison result is fed back in real time to adjust a supply of one or more reactants. The system and method provide real time control over the deposition process and/or reduce the number of wafers produced that do not meet processing target values.

System and method for real time deposition process control based on resulting product detection

A method for supplying a source gas to a processing chamber for forming a film on a substrate in the processing chamber includes: heating a carrier gas; bubbling the heated carrier gas in a liquid source disposed in a container to form a vapor source; and supplying a source gas including the vapor source and the heated carrier gas into the processing chamber for forming the film.

Growing community of inventors

Gyeonggi-do, South Korea

Jai-Dong Lee