Samsung Electronics Co., Ltd.

Jahyun Koo

Seokyong Hong

Dahsom Kim

Hyeokjong Lee

Soonik Cho

Yooseung Jung

Junyoung Kil

Donghoon Sung

An image sensor includes a pixel array, a ramp signal generating circuit configured to output a first reference ramp signal of a first slope as a first ramp signal in a first period and a second reference ramp signal of a second slope as the first ramp signal in a second period, an offset voltage sampling circuit configured to, to sample an offset voltage based on a DC level of the first reference ramp signal, to output the first ramp signal in the first period, and to output a signal obtained by adding the offset voltage to the first ramp signal as a second ramp signal in the second period, a buffer configured to buffer the first ramp signal and the second ramp signal, and an ADC circuit configured to compare a pixel signal from the pixel array with the first ramp signal or the second ramp signal.

Image sensor and electronic device including the same

An image sensor device includes a first pixel located at a first row, a first select transistor, a second pixel located at a second row, a second select transistor, the second row being different from the first row, and a column line connected to both the first pixel and the second pixel, and during a first time period, a floating diffusion node of the first pixel is reset, and during a second time period, the second select transistor is turned on, and a first voltage is applied to the column line through the second select transistor, the second time period is included in the first time period, and the first voltage is determined based on a voltage of a reset floating diffusion node of the second pixel.

Image sensor device and operation method thereof

An image sensor includes a pixel sensor outputting an analog sampling signal; a sampling unit comparing the sampling signal and a ramp signal, and outputting a comparison signal that is time-axis length information; and a counter counting a length of the comparison signal based on a clock signal and first and second complement control signals. The counter includes an AND gate ANDing the comparison signal and the clock signal; and a counting unit triggered at a falling edge of the AND gate output to output a count value. The counting unit includes a complement operation controller storing an inverted count value that is an inversion of the count value in response to the first complement control signal, and outputting the inverted count value in response to the second complement control signal; and a D-flip-flop that is set or reset depending on the inverted count value, and outputs the count value.

Counter circuit and image sensor including the same

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Yongin-si, South Korea

Jahyun Koo