Samsung Electronics Co., Ltd.

Jahoon Jin

Soomin Lee

Kyunghwan Min

Sangho Kim

Sodam Ju

Sang-Ho Kim

Jihoon Lim

Hyun Su Chea

Disclosed is a receiver of a serial interface, comprising, a first multiplexer configured to select one of a data signal and a first reference voltage in response to an enable signal, a second multiplexer configured to select one of the first reference voltage and a second reference voltage in response to the enable signal, a comparator receiving an output of the first multiplexer to a positive input terminal and an output of the second multiplexer to a negative input terminal, and a reference generator configured to generate the second reference voltage and to generate the first reference voltage from the second reference voltage using an unity gain buffer.

Serial interface receiver and offset calibration method thereof

Disclosed is a frequency detector. The frequency detector includes a first flip-flop sampling a clock signal based on a data signal to generate a first signal, a second flip-flop sampling a delayed-phase component of the clock signal based on the data signal or sampling the clock signal based on a delayed-phase component of the data signal to generate a second signal, a third flip-flop generating a third signal representing a polarity of a frequency difference between a data rate of the data signal and a frequency of the clock signal based on the first signal and the second signal, and a delay cell generating the delayed-phase component of the clock signal or the delayed-phase component of the data signal. The delayed-phase component has a delay amount set to a value smaller than about 0.25 UI.

Frequency detector and operating method thereof

Provided is a method of correcting a clock, the method including receiving a first clock, a second clock, a third clock, and a fourth clock, correcting each of a second rising edge of the second clock, a third rising edge of the third clock, and a fourth rising edge of the fourth clock based on a first rising edge of the first clock, and correcting each of a first falling edge of the first clock, a second falling edge of the second clock, a third falling edge of the third clock, and a fourth falling edge of the fourth clock based on a first rising edge of the first clock.

Clock edge correcting device and operating method thereof

A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n−1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n−1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n−1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n−1 first signals transitions from the second signal level to the first signal level, to output n−1 second signals.

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Suwon-si, South Korea

Jahoon Jin