Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Jagdish Sabde

Sagar Magia

Jayavel Pachamuthu

Rajan Paudel

Daniel Joseph Linnen

Avinash Rajagiri

Kirubakaran Periyannan

Khanh Vinh Nguyen

Srikar Peesari

Shantanu Gupta

Ankitkumar Babariya

Peter Rabkin

Dongxiang Liao

Ashish Ghai

Deepak Bharadwaj

Tien-Chien Kuo

Deepak Raghu

Shrikar Bhagath

Mrinal Kochar

Sukhminder Singh Lobana

Pradhyumna Ravikirthi

Ashish Pal Singh Ghai

Abhinav Anand

A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Partial memory die with inter-plane re-mapping

Aspects of the disclosure provide for reducing a temperature of one or more non-volatile memory (NVM) dies of a solid state drive (SSD). The methods and apparatus detect a temperature of one or more NVM dies of a plurality of NVM dies of the SSD, the plurality of NVM dies including at least one parity NVM die, and determine that the one or more NVM dies is overheated when the detected temperature is at or above a threshold temperature. If the detected temperature is at or above the threshold temperature, the methods and apparatus redirect parity data designated for the at least one parity NVM die to the one or more overheated NVM dies. By repurposing the one more overheated NVM dies to store the parity data, the repurposed dies will experience less activity, and therefore, generate less heat without throttling or reducing the workload capability of the dies.

Parity relocation for reducing temperature throttling

A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Partial memory die

Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.

High-speed data path testing techniques for non-volatile memory

Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure.

Techniques for determining local interconnect defects

Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.

NAND structure with tier select gate transistors

Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb.

Erase stress and delta erase loop count methods for various fail modes in non-volatile memory

A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings, filled with first support pillar structures and sacrificial pillar structures, respectively, are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed thereabove. Second support openings and second memory openings are formed through the second tier structure such that the second support openings do not overlap with the first support pillar structures and the second memory openings overlie the sacrificial pillar structures. Inter-tier memory openings are formed by removal of the sacrificial pillar structures. Memory stack structures and second support pillar structures are formed in the inter-tier memory openings and the second support openings, respectively.

Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof

A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns. The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.

Stress patterns to detect shorts in three dimensional non-volatile memory

A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Determination of word line to word line shorts between adjacent blocks

For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program, including comparing the amount of current drawn by different sets of memory cells during different write operations. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.

Current based detection and recording of memory hole-interconnect spacing defects

Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example implementation, during a programming operation, the number of program loops used to complete programming or reach another programming milestone for WLn are counted. If the number of program loops exceeds a loop count limit, the memory cells of WLn+1 are evaluated to determine whether a short circuit is present. The evaluation involves a read operation which counts erased state memory cells in the upper tail of the Vth distribution of WLn+1. If the count exceeds a bit count limit, it is concluded that a short circuit exits between WLn and WLn+1, and a corrective action is taken. The loop count limit is adjusted lower as the number of program-erase cycles increases.

Word line look ahead read for word line to word line short detection

Detecting defects in select gates of memory cell strings is disclosed. An electrical short between adjacent select gates may be detected. The select gate may comprises a transistor having an adjustable threshold voltage. An operation configured to change a threshold voltage of one select transistor and to maintain a threshold voltage of an adjacent select transistor may be performed. The select transistors may be flagged in response to the threshold voltage of either select transistor failing to meet a target threshold voltage in response to the operation. The operation may be an erase operation or a program operation.

Select gate defect detection

A method is provided for programming a memory cell connected to a selected word line in a memory device. The method includes performing one programming pass of a multi-pass programming operation for the memory cell, wherein a first set of program pulses is applied to the selected word line during the one programming pass, determining a number of the program pulses applied to the selected word line during the one programming pass, determining a difference between the determined number of program pulses applied to the selected word line during the one programming pass and a predetermined number of program pulses, adjusting a parameter of a second set of program pulses for the another programming pass based on the determined difference, and performing the another programming pass for the set of memory cells, wherein the second set of program pulses is applied to the selected word line during the another programming pass.

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Fremont, CA, United States of America

Jagdish Sabde