Kla Tencor Corporation

Jagdish Chandra Saraswatula

Saibal Banerjee

Ashok V Kulkarni

Arpit Yati

Martin Plihal

Santosh Bhattacharyya

Andrew Cross

Hari Pathangi

Shivam Agarwal

Hari Sriraman Pathangi

Defect location accuracy can be increased using shape based grouping with pattern-based defect centering. Design based grouping of defects on a wafer can be performed. A spatial distribution of the defects around at least one structure on the wafer, such as a predicted hot spot, can be determined. At least one design based defect property for a location around the structure can be determined. The defects within an x-direction threshold and a y-direction threshold of the structure may be prioritized.

Defect location accuracy using shape based grouping guided defect centering

Systems and methods for determining location of critical dimension (CD) measurement or inspection are disclosed. Real-time selection of locations to take critical dimension measurements based on potential impact of critical dimension variations at the locations can be performed. The design of a semiconductor device also can be used to predict locations that may be impacted by critical dimension variations. Based on an ordered location list, which can include ranking or criticality, critical dimension can be measured at selected locations. Results can be used to refine a critical dimension location prediction model.

Inspection-guided critical site selection for critical dimension measurement

A wafer topography measurement system can be paired with a scanning electron microscope. A topography threshold can be applied to wafer topography data about the wafer, which was obtained with the wafer topography measurement system. A metrology sampling plan can be generated for the wafer. This metrology sampling plan can include locations in the wafer topography data above the topography threshold. The scanning electron microscope can scan the wafer using the metrology sampling plan and identify defects.

Guided scanning electron microscopy metrology based on wafer topography

Methods and systems for shape metric based scoring of wafer locations are provided. One method includes selecting shape based grouping (SBG) rules for at least two locations on a wafer. For one of the wafer locations, the selecting step includes modifying distances between geometric primitives in a design for the wafer with metrology data for the one location and determining metrical complexity (MC) scores for SBG rules associated with the geometric primitives in a field of view centered on the one location based on the distances. The selecting step also includes selecting one of the SBG rules for the one location based on the MC scores. The method also includes sorting the at least two locations on the wafer based on the SBG rule selected for the at least two locations.

Shape metric based scoring of wafer locations

Techniques are provided that can select defects based on criticality of design pattern as well as defect attributes for process window qualification (PWQ). Defects are sorted into categories based on process conditions and similarity of design. Shape based grouping can be performed on the random defects. Highest design based grouping scores can be assigned to the bins, which are then sorted. Particular defects can be selected from the bins. These defects may be reviewed.

Criticality analysis augmented process window qualification sampling

Shape primitives are used for inspection of a semiconductor wafer or other workpiece. The shape primitives can define local topological and geometric properties of a design. One or more rules are applied to the shape primitives. The rules can indicate presence of a defect or the likelihood of a defect being present. A rule execution engine can search for an occurrence of the shape primitives covered by the at least one rule.

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Puttaparthi, India

Jagdish Chandra Saraswatula