International Business Machines Corporation

Jagannathan Narasimhan

Louise Helen Trevillyan

Anthony DeGroff Drumm

Amir H Farrahi

Sebastian Theodore Ventrone

David James Hathaway

John Maxwell Cohn

Lakshmi Narasimha Reddy

Alvar Antonio Dean

Scott Alan Tetreault

Thomas M Lepsic

Brian C Wilson

Renato Fernandes Hentschke

Marcelo De Oliveira Johann

Ricardo Augusto De Luz Reis

Chin Ngai Sze

Ruchir Puri

Minsik Cho

Haoxing Ren

Sharad Mehrotra

Haifeng Qian

Matthew Mantell Ziegler

Hua Xiang

Albert E Ruehli

Victor N Kravets

Frank Musante

Dorothy Kucar

Smita Krishnaswamy

A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

Task-based multi-process design synthesis

A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.

Task-based multi-process design synthesis with notification of transform signatures

A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.

Task-based multi-process design synthesis with reproducible transforms

Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.

Converged large block and structured synthesis for high performance microprocessor designs

A method of producing a flexible timing-driven routing tree is provided. Two or more target nodes are sorted in accordance with data criticality. A source-sink grid is built from one or more source nodes and the two or more target nodes. An initial routing tree is built comprising the one or more source nodes. A routing tree generation algorithm is executed on the initial routing tree, utilizing the sorted two or more target nodes and the source-sink grid in accordance with a user-defined timing factor to construct a flexible timing-driven routing tree. The user-defined timing factor specifies an extent of isolation for a routing path from a given one of the one or more source nodes to a given one of the two or more target nodes.

Methods and apparatus for providing flexible timing-driven routing trees

An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability &#x3c6;per clock cycle that is no less than a pre-selected minimum same-direction switching probability &#x3c6;or has an opposite-direction switching probability &#x3c6;per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability &#x3c6;. The first wire and the second wire satisfies at least one mathematical relationship involving Land Wwhere Wis defined as a spacing between the first wire and the second wire, and Lis defined as a common run length of the first wire and the second wire.

Wiring optimizations for power

An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

A method is provided for computing signal and switching probabilities at an output of a logic circuit in a network having multiple logic circuits. The method for computing the signal and switching probabilities includes steps of creating a truth table for a logic circuit where the truth table has entries respectively corresponding to signals at inputs of the logic circuit, choosing in sequence one of entries each representing switching of a signal at the output of the circuit, determining whether a signal at an input corresponding to the chosen entry is at logic high, assigning an event probability representing that the signal is at logic high, and accumulating event probabilities respectively assigned to signals at inputs corresponding to the chosen entries to produce the signal probability at the output of the circuit.

Method for propagating switching activity information in digital combinatorial networks

An apparatus and method is presented for capacitance analysis in chip environments for arbitrary geometries. It uses a process which combines 2-dimensional ascertainments where the length is chosen to fit the solution. Also, the required accuracy may be limited to be within an error range. The technique is also applicable for the analysis of three dimensional capacitances, and importantly also for a mixture of two and three dimensional capacitance ascertainments. In an embodiment the process divides the space into a set of subspaces. The capacitance value for the subspaces are determined using the parallel plate capacitance formula.

Modeling and processing of on-chip interconnect capacitance

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Millwood, NY, United States of America

Jagannathan Narasimhan