Legerity, Inc.

Advanced Micro Devices Corporation

Zarlink Semiconductor Limited

Jagannathan Bharath

David N Larson

Sharif Mohammad Sazzad

Tony E Sawan

Sandhya Sharma

A method and apparatus are provided for accessing data. The method includes defining a first portion of a memory for receiving data and providing a memory request to transfer data from a source to the first portion of the memory defined to receive the data. The method further includes transferring a portion of data from the source to the first portion of the memory, wherein the size of the portion of the data substantially corresponds to the size of the first portion of the memory.

Method and apparatus for accessing variable sized blocks of data

An apparatus is provided that includes a data controller, a subscriber line audio-processing circuit, and a controller. The data controller includes an input terminal and an output terminal capable of providing packet data. The subscriber line audio-processing circuit is capable of providing signals in a voice band. The controller is capable of transmitting at least one of signals in the voice band from the subscriber line audio-processing circuit and the packet data from the output terminal of the data controller.

Apparatus for transmitting and receiving signals

A method and apparatus are provided for encrypting a stream of data transmitted within a frame. The method includes determining a first initialization state in a first preselected interval, and determining the first initialization state in a second preselected interval, wherein the second preselected interval is less than the first preselected interval. The method includes generating a key stream in response to determining the first initialization state in the second preselected interval, and encrypting at least one bit of the stream of data with at least one bit of the key stream.

Method and apparatus for encryption and decryption

A method and apparatus are provided, where the method includes defining a first portion of a memory for receiving data, providing a memory request to transfer data from a source to the first portion of the memory defined to receive the data, and transferring a portion of data from the source to the first portion of the memory according to a priority scheme that determines the sequence of the data transfer, wherein the size of the portion of the data substantially corresponds to the size of the first portion of the memory. The method also includes associating a frame with at least one corresponding memory location containing data in the first portion of the memory, transmitting at least a portion of data from the first portion of the memory within the frame, and receiving an acknowledgement in response to transmitting the data within the frame.

Method and apparatus for prioritizing packet data transmission and reception

A method and apparatus are provided, where the method and apparatus include associating a frame with at least one corresponding memory location that contains data, transmitting the data within the frame to a peer station, receiving an acknowledgement in response to transmitting the data within the frame from the peer station, analyzing the acknowledgement to determine if the data within the frame transmits successfully, and updating the corresponding memory location with new data in response to determining if the data transmits successfully.

Method and apparatus for managing data transfer and acknowledgements

A memory-efficient system and method for generating data blocks &ldquo;on demand&rdquo; for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

System and method for bit interleaving of full-rate speech data

A memory-efficient system and method for generating data blocks 'on demand' for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

A memory-efficient system and method for generating data blocks 'on demand' for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded half-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

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El Dorado Hills, CA, United States of America

Jagannathan Bharath