Texas Instruments Corporation

Jagadeesh Sankaran

Ching-Yu Hung

Gary L Swoboda

Brian Cruickshank

Oliver P Sohm

Shinri Inamori

Peter Chang

David J Hoyle

Elana D Granston

Joseph R Zbiciak

Jeremiah E Golston

Steven D Krueger

Shraddha Gondkar

A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

Vector table load instruction with address generation field to access table offset value

Processor with table lookup processing unit

A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.

Processor with instruction variable data distribution

A method (and system) of determining a local binary pattern in an image includes selecting an orientation. For each pixel in the image, the method further includes determining a binary decision for each such pixel relative to one neighboring pixel of the orientation, selecting a new orientation, and repeating the determination of the binary decision for each pixel in the image relative to one neighboring pixel of the newly selected orientation.

Vector processor calculation of local binary patterns

In accordance with at least some embodiments, a system includes a processing entity configured to run multiple threads. The system also includes a direct memory access (DMA) engine coupled to the processing entity, the DMA engine being configured to track DMA in-flight status information for each of a plurality of DMA channels. The processing entity is configured to manage overlapping DMA requests to a DMA channel of the DMA engine based on said DMA in-flight status information.

Methods and systems for direct memory access (DMA) in-flight status

In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.

On-demand predicate registers

This invention decodes coefficient magnitudes in compressed video data using a selected context and speculatively decodes a coefficient sign. The next context selection depends upon a number of iterations. This invention confirms the speculatively decoded coefficient sign upon completion of the magnitude decode. This invention operates in a loop until reaching the number of significant coefficients within the block. The method exits the loop and decodes an escape code if an iteration count is greater than a predetermined number. An embodiment of this invention collects both a count up and a count down in an escape code decode in one loop. An embodiment of this invention estimates the number of significant coefficients in a block and selects the inventive or a prior art decode.

Method of CABAC coefficient magnitude and sign decoding suitable for use on VLIW data processors

This invention decodes a next significance symbol using a selected context. The invention operates in a loop for each symbol decode for a whole block until the number of decoded map elements reaches a maximum number of coefficients for the block type or a last significant coefficient marker is decoded updating loop variables accordingly. This invention counts the number of decoded significance symbols indicating a significant coefficient and stores the locations of such significant coefficients in an array. An embodiment of this invention estimates the number of significant coefficients in a block and selects the inventive method or a prior art decode method.

Method of CABAC significance MAP decoding suitable for use on VLIW data processors

An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information is from caches on different cache levels associated with a common address. The processor also displays the information by way of a graphical user interface (GUI). The GUI displays a portion of the information using a mark-up technique different from that used to display remaining portions of the information.

Displaying cache information using mark-up techniques

An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to selectively bypass a portion of the information specified by a user of the software and to provide non-bypassed information to the user and not said bypassed portion.

Cache inspection with inspection bypass feature

An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, the information associated with a common address. The software also causes the processor to provide the information to a user of the software. The information comprises cache level and cache type information associated with a particular cache from one of the different cache levels.

Providing information associated with a cache

This invention prevents illegal memory address faults on speculative data loads. Circular addressing of the address pointer limits memory access to a range of addresses including all addresses used by the address pointer and not including any invalid addresses. The invention uses circular addressing hardware, if available on the data processor. If not available, this invention simulates circular addressing. This invention permits loads to be issued earlier than if predication were used and allows already predicated loads to be speculated without the overhead of a compound predicate. This invention can be used on processors without hardware supporting speculation.

Speculative data loading using circular addressing or simulated circular addressing

This invention modifies an irregular software pipelined loop conditioned upon data in a condition register in a compiler scheduled very long instruction word data processor to prevent over-execution upon loop exit. The method replaces a register modifying instruction with an instruction conditional upon the inverse condition register if possible. The method inserts a conditional register move instruction to a previously unused register within the loop if possible without disturbing the schedule. Then a restoring instruction is added after the loop. Alternatively, both these two functions can be performed by a delayed register move instruction. Instruction insertion is into a previously unused instruction slot of an execute packet. These changes can be performed manually or automatically by the compiler.

Mechanism for pipelining loops with irregular loop control

A syndrome evaluation with partitioning of a received block of symbols into subsets and interleaved partial syndrome evaluations to overcome multiplier latency. Parallel syndrome evaluations with a parallel multiplier.

Error correction structures and methods

This invention is applicable to filtering block artifacts of macroblock and block oriented video compression. This invention computes all possible filter results speculatively and simultaneously in parallel, computes conditions for application of corresponding filter results simultaneously in parallel, and writes filter results to memory conditionally dependent upon computed corresponding conditions. This invention permits effective block filtering on a very long instruction word data processor.

Growing community of inventors

Allen, TX, United States of America

Jagadeesh Sankaran