Intel Corporation

Jagadeesh Chandra Salaka

Gururaj Shamanna

Abhishek A Sharma

Iqbal Rajwani

Pascal Meinerzhagen

Naveen Kumar M

Harishankar Sahu

Purna C Nayak

Sravan K Puchakayala

Mitesh Goyal

Circuits for optimizing the duration of a sense amp enable signal in a memory device such as SRAM.

Apparatus and method to optimize sense-amp enable pulse-width in SRAM arrays

A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.

Low power clock gate circuit

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Bengaluru, India

Jagadeesh Chandra Salaka